AD7982BRMZ Analog Devices Inc, AD7982BRMZ Datasheet - Page 19

• Manufacturer Part Number: AD7982BRMZ
• Description: IC ADC 18BIT 1MSPS PULSAR 10MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7982BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Converting a Single-Ended Signal with AD7982 Differential PulSAR ADC (CN0032) Precision Single-Supply Differential ADC Driver for Industrial-Level Signals (CN0180)
• Number Of Bits: 18
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 8.6mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 18bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Supply Current: 350nA
• Package: 10MSOP
• Resolution: 18 Bit
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Serial (3-Wire, 4-Wire, SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 98(Typ) dB
• Polarity Of Input Voltage: Bipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7982s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7982s is shown in
Figure 33, and the corresponding timing is given in Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
SDI(CS1)
SDI(CS2)
ACQUISITION
SDO
CNV
SCK
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
SDI
Figure 34. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Figure 33. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
AD7982
D17
1
CNV
SCK
t
HSDO
D16
2
SDO
D15
3
t
DSDO
t
SCKL
t
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SCKH
16
SDI
t
SCK
AD7982
17
D1
CNV
SCK
t
CYC
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7982 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided it has an acceptable hold time.
After the 18
occurs first), SDO returns to high impedance and another
AD7982 can be read.
18
D0
ACQUISITION
SDO
t
ACQ
th
SCK falling edge or when SDI goes high (whichever
D17
19
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
D16
20
34
35
D1
36
D0
t
DIS
AD7982