AD9255BCPZ-80 Analog Devices Inc, AD9255BCPZ-80 Datasheet - Page 30

• Manufacturer Part Number: AD9255BCPZ-80
• Description: IC ADC 14BIT 80MSPS 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9255BCPZ-80

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Number Of Converters: 1
• Power Dissipation (max): 248mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 80MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9255
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522 clock drivers offer excellent jitter
performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, drive the CLK+ pin directly from a CMOS gate, and bypass
the CLK− pin to ground with a 0.1 μF capacitor (see Figure 79).
CLOCK
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9255 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9255. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
enabled. Jitter in the rising edge of the input is still of paramount
concern and is not easily reduced by the internal stabilization
circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency increase
or decrease before the DCS loop is relocked to the input signal.
During the time period that the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the duty
cycle of the input clock signal. In such applications, it may be
appropriate to disable the duty cycle stabilizer. The DCS can
1
INPUT
50Ω RESISTOR IS OPTIONAL.
Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50Ω
0.1µF
1
V
CC
1kΩ
1kΩ
AD95xx
CMOS DRIVER
CLOCK
CLOCK
INPUT
INPUT
OPTIONAL
Figure 78. Differential LVDS Sample Clock (Up to the Rated Sample Rate)
0.1µF
100Ω
50kΩ
0.1µF
CLK+
CLK–
0.1µF
0.1µF
50kΩ
AD9255
ADC
AD95xx
LVDS DRIVER
Rev. A | Page 30 of 44
also be disabled in some cases when using the input clock
divider circuit, see the Input Clock Divider section for addi-
tional information. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
The DCS is enabled by setting the SDIO/DCS pin high when
operating in the external pin mode (see Table 12). If the SPI
mode is enabled, the DCS is enabled by default and can be
disabled by writing a 0x00 to Address 0x09.
Input Clock Divider
The AD9255 contains an input clock divider with the ability to
divide the input clock by integer values between 2 and 8. For
clock divide ratios of 2, 4, 6, or 8, the duty cycle stabilizer (DCS)
is not required because the output of the divider inherently pro-
duces a 50% duty cycle. Enabling the DCS with the clock divider in
these divide modes may cause a slight degradation in SNR so
disabling the DCS is recommended. For other divide ratios,
divide-by-3, divide-by-5, and divide-by-7 the duty cycle output
from the clock divider is related to the input clock’s duty cycle.
In these modes, if the input clock has a 50% duty cycle, the DCS
is again not required. However, if a 50% duty cycle input clock
is not available the DCS must be enabled for proper part
operation.
To synchronize the AD9255 clock divider, use an external sync
signal applied to the SYNC pin. Bit 1 and Bit 2 of Register 0x100
allow the clock divider to be resynchronized on every SYNC
signal or only on the first SYNC signal after the register is written.
A valid signal at the SYNC pin causes the clock divider to reset
to its initial state. This synchronization feature allows multiple
parts to have their clock dividers aligned to guarantee simulta-
neous input sampling. If the SYNC pin is not used, it should be
tied to AGND.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
jitter (t
In this equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as illustrated in Figure 80.
SNR
100Ω
JRMS
0.1µF
0.1µF
HF
) can be calculated by
= −10 log[(2π × f
CLK+
CLK–
AD9255
ADC
LF
) at a given input frequency (f
INPUT
× t
JRMS
)
2
+ 10
(
−
SNR
INPUT
LF
/
10
) due to
)
]