AD7650AST Analog Devices Inc, AD7650AST Datasheet - Page 6

• Manufacturer Part Number: AD7650AST
• Description: IC ADC 16BIT 570KSPS 48-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7650AST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 77mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: EVAL-AD7650CBZ - BOARD EVALUATION FOR AD7650

AD7650
Pin No.
1
2
3, 40–42,
44–48
4
5
6
7
8
9–12
13
14
15
Mnemonic
AGND
AVDD
NC
DGND
OB/2C
WARP
IMPULSE
SER/PAR
DATA[0:3]
DATA[4]
or EXT/INT
DATA[5]
or INVSYNC
DATA[6]
or INVSCLK
DO
Type
P
P
DI
DI
DI
DI
DI
DI/O
DI/O
DI/O
NC = NO CONNECT
Description
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
Must be tied to the ground where DVDD is referred.
Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from
its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/PAR.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock
is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized
to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of
the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
IMPULSE
SER/PAR
OB/2C
DGND
WARP
AGND
AVDD
48-Lead LQFP and 48-Lead LFSCP
NC
PIN FUNCTION DESCRIPTIONS
D0
D1
D2
D3
10
11
12
1
2
3
4
5
6
7
8
9
PIN CONFIGURATION
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44
(ST-48 and CP-48)
PIN 1
IDENTIFIER
(Not to Scale)
AD7650
TOP VIEW
43 42 41 40
39 38 37
36
35
34
33
32
30
29
28
27
26
25
31
D12
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13