AD1870AR-REEL Analog Devices Inc, AD1870AR-REEL Datasheet
AD1870AR-REEL
Specifications of AD1870AR-REEL
Related parts for AD1870AR-REEL
AD1870AR-REEL Summary of contents
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FEATURES Single 5 V Power Supply Single-Ended Dual-Channel Analog Inputs 92 dB (Typ) Dynamic Range 90 dB (Typ) S/(THD + N) 0.006 dB Decimator Pass-Band Ripple Fourth Order, 64 Oversampling - Modulator Three-Stage, Linear-Phase Decimator 256 f or 384 ...
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AD1870–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages Ambient Temperature ) [256 × f Input Clock (f ] CLKIN S Input Signal Measurement Bandwidth Load Capacitance on Digital Outputs Input Voltage Input Voltage ...
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DIGITAL I/O Input Voltage Input Voltage Input Leakage ( Input Leakage ( Output Voltage ...
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... AGND to DGND Reference Voltage Soldering (10 sec) Model AD1870AR AD1870AR–REEL EVAL-AD1870EB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1870 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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PIN FUNCTION DESCRIPTIONS Input/ Pin Pin Output Name Description 1 I/O LRCK Left/Right Clock 2 I/O WCLK Word Clock 3 I/O BCLK Bit Clock Digital Supply DGND1 Digital Ground 6 I ...
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AD1870 –Typical Performance Characteristics 0 –20 –40 –60 –80 –100 –120 –140 FREQUENCY – kHz TPC 1. 1 kHz Tone at –0.5 dBFS (16 k-Point FFT) 0 –20 –40 –60 –80 –100 ...
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NORMALIZED TPC 7. Digital Filter Signal Transfer Function Continued from Page 1 The flexible serial ...
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AD1870 44.1 kHz. The stop-band attenuation is sufficient to eliminate modulator quantization noise from affecting the output. Low pass-band ripple prevents the digital filter from coloring the audio signal. See TPC 7 for the digital filter’s characteristics. The output from ...
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The AD1870 achieves its specified performance without the need for user trims or adjustments. This is accomplished through the use of on-chip automatic offset calibration that takes place immediately following reset. This procedure nulls out any off- sets in the ...
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AD1870 Layout and Decoupling Considerations Obtaining the best possible performance from the AD1870 requires close attention to board layout. Adhering to the follow- ing principles will produce typical values dynamic range and 90 dB S/(THD + N) ...
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Figure 5 shows a circuit for obtaining improvement in dynamic range by using both channels of a single AD1870 with a mono input. A stereo implementation would require using two AD1870s and using the recommended input structure ...
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AD1870 Serial Port Data Timing Sequences The RDEDGE input (Pin 6) selects the bit clock (BCLK) polarity. RDEDGE HI causes data to be transmitted on the BCLK falling edge and valid on the BCLK rising edge; RDEDGE LO causes data ...
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Timing Parameters For master modes, a BCLK transmitting edge (labeled “XMIT”) will be delayed from a CLKIN rising edge Figure 17. A LRCK transition will be delayed from a BCLK transmitting edge WCLK ...
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AD1870 LRCK INPUT BCLK RDEDGE = LO INPUT BCLK RDEDGE = HI PREVIOUS DATA SOUT ZEROS MSB-14 LSB OUTPUT WCLK OUTPUT LEFT TAG TAG MSB LSB OUTPUT Figure 7. Serial Data Output Timing: Slave Mode, Right-Justified ...
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LRCK INPUT BCLK RDEDGE = INPUT BCLK RDEDGE = HI LEFT DATA SOUT ZEROS MSB OUTPUT MSB-1 WCLK OUTPUT LEFT TAG TAG MSB LSB OUTPUT Figure 10. Serial Data Output Timing: Slave Mode, I LRCK ...
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AD1870 LRCK OUTPUT BCLK RDEDGE = LO OUTPUT BCLK RDEDGE = HI LEFT DATA SOUT ZEROS MSB OUTPUT MSB-1 WCLK OUTPUT LEFT TAG TAG MSB LSB OUTPUT Figure 13. Serial Data Output Timing: Master Mode, Left-Justified ...
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LRCK INPUT BCLK RDEDGE = LO INPUT 32 1 BCLK RDEDGE = HI PREVIOUS DATA SOUT LSB OUTPUT MSB-14 WCLK OUTPUT LEFT TAG TAG MSB OUTPUT Figure 16. Serial Data Output Timing: Slave Mode Hl, R ...
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AD1870 PIN 1 0.0118 (0.30) 0.0040 (0.10) AD1870–Revision History Location 6/02—Data Sheet changed from REV REV. A. Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . ...
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