AD7885ABP Analog Devices Inc, AD7885ABP Datasheet - Page 11

IC ADC 16BIT SAMPLING HS 44-PLCC

AD7885ABP

Manufacturer Part Number
AD7885ABP
Description
IC ADC 16BIT SAMPLING HS 44-PLCC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7885ABP

Rohs Status
RoHS non-compliant
Number Of Bits
16
Sampling Rate (per Second)
166k
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
325mW
Voltage Supply Source
Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-PLCC

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REV. E
AD7884/AD7885 PERFORMANCE
Linearity
The linearity of the AD7884/AD7885 is determined by the
on-chip 16-bit D/A converter. This is a segmented DAC that is
laser trimmed for 16-bit DNL performance to ensure that there
are no missing codes in the ADC transfer function. Figure 13
shows a typical INL plot for the AD7884/AD7885.
Noise
In an A/D converter, noise exhibits itself as code uncertainty in
dc applications and as the noise floor (in an FFT, for example)
in ac applications.
In a sampling A/D converter like the AD7884/AD7885, all
information about the analog input appears in the baseband
from dc to 1/2 the sampling frequency. An antialiasing filter will
remove unwanted signals above f
converter wideband noise will alias into the baseband. In the
AD7884/AD7885, this noise is made up of sample-and-hold noise
and A/D converter noise. The sample-and-hold section contrib-
utes 51 µV rms and the ADC section contributes 59 µV rms.
These add up to a total rms noise of 78 µV. This is the input
referred noise in the ± 3 V analog input range. When operating
in the ± 5 V input range, the input gain is reduced to –0.6. This
means that the input referred noise is now increased by a factor
of 1.66 to 120 µV rms.
Figure 14 shows a histogram plot for 5000 conversions of a dc
input using the AD7884/AD7885 in the ± 5 V input range. The
analog input was set as close as possible to the center of a code
transition. All codes other than the center code are due to the
ADC noise. In this case, the spread is six codes.
Figure 13. AD7884/AD7885 Typical Linearity Performance
2.0
1.5
1.0
0.5
0
0
16384
OUTPUT CODE
32768
S
/2 in the input signal, but the
49152
V
V
T
DD
SS
A
= 25 C
= –5V
= +5V
65535
–11–
If the noise in the converter is too high for an application, it can
be reduced by oversampling and digital filtering. This involves
sampling the input at a higher than the required word rate
and then averaging to arrive at the final result. The very fast
conversion time of the AD7884/AD7885 makes it very
suitable for oversampling. For example, if the required input
bandwidth is 40 kHz, the AD7884/AD7885 could be
oversampled by a factor of 2. This yields a 3 dB
improvement in the effective SNR performance. The noise
performance in the ±5 V input range is now effectively 85 µV rms,
and the resultant spread of codes for 2500 conversions will be four.
This is shown in Figure 15.
Figure 14. Histogram of 5000 Conversions of a DC Input
Figure 15. Histogram of 2500 Conversions of a DC Input
Using a × 2 Oversampling Ratio
3000
2000
1000
1500
1000
500
0
0
(X – 2)
(X – 1)
(X – 1)
(X)
CODE
CODE
AD7884/AD7885
(X)
(X + 1)
(X + 1)
(X + 2)
(X + 2)
(X + 3)

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