AD9483KS-100 Analog Devices Inc, AD9483KS-100 Datasheet
AD9483KS-100
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AD9483KS-100 Summary of contents
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FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal 2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or ...
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... Full IV 0.4 Full IV 0 Full IV 1.5 Full VI Full VI 25°C V 2.5 –2– AD9483KS-100 Max Min Typ Max 8 1.25/–1.0 0.8 1.25/–1.0 1.50/–1.0 1.50/–1.0 1.50/–1.50 0.9 1.50/–1.50 LSB 1.75/–1.75 1.75/–1.75 LSB Guaranteed ± 2 ± ...
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... V 7.0 25°C I 6.4 6.8 25°C V 6.8 25° 25° 25° 25° 25° 25° Full 10°C/W, θ = 17°C/W, θ –3– AD9483KS-100 Max Min Typ Max V 2 0 – 0.05 DD 0.05 0.05 Binary 215 215 60 60 1.3 1.0 1 100 20 100 1.5 1.5 ...
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... V – Parameter is a typical value only. VI – 100% production tested at 25°C; guaranteed by design and characterization testing. Model AD9483KS-100 AD9483KS-140 AD9483/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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Pin Number Mnemonic 10, 20, 30, 40, 50, 60, 70, 73, 77, 78, 80, 81, 95, 96, 100 GND 2 ENCODE ENCODE DCO DCO 9 11, 21, 31, 41, 51, 61, ...
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AD9483 GND ENCODE ENCODE DS DS GND GND DCO DCO GND ...
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TIMING SAMPLE N SAMPLE N–1 AIN ENCODE ENCODE D7–D0 DATA N–5 CLOCK OUT CLOCK OUT SAMPLE N–1 AIN SAMPLE N– ENCODE ENCODE t HDS t SDS DS DS PORT A DATA N–7 DATA N–7 D7–D0 OR ...
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AD9483 EQUIVALENT CIRCUITS AIN AD9483 Figure 3. Equivalent Analog Input Circuit V CC VREF IN 500 2k AD9483 Figure 4. Equivalent Reference Input Circuit AD9483 300 ENCODE DS Figure 5. Equivalent Encode and Data Select Input Circuit AD9483 DEMUX Figure ...
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NYQUIST FREQUENCY (70MHz) –2 –2.5 –3 –3.5 –4 –4.5 – 100 150 200 250 f – MHz IN TPC 1. Frequency Response: f –70 –60 –50 –40 –30 –20 – 2.5 5 ...
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AD9483 9 8 6.5 6 5 LOAD CAPACITANCE – pF TPC 7. Clock Output Delay vs. Capacitance ...
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MSPS S TPC 13. SNR vs –75 –70 3RD HARMONIC –65 –60 2ND HARMONIC –55 – ...
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AD9483 46 SNR f = 140MSPS 19.3MHz 25% 28% 31% 38% 45% 52% 1.8 2 2.2 2.7 3.2 3.7 ENCODE DUTY CYCLE – % ENCODE PULSEWIDTH – ns ...
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APPLICATION NOTES Theory of Operation The AD9483 combines Analog Devices’ patented MagAmp bit- per-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on board reference and input ...
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AD9483 ADC Offset Control The offset for each of the three ADCs can be independently controlled. For a single-ended analog input where the analog input is connected to a reference, offset can be adjusted simply by adjusting the dc voltage ...
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Data Sync The Data Sync input, DS, is required to be driven for most applications to guarantee at which output port a given sample will appear. When DS is held high, the ADC data outputs and clock outputs do not ...
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AD9483 EVALUATION BOARD The AD9483 evaluation board offers an easy way to test the AD9483. It provides biasing for the analog input, it generates the output latch clocks for Single Mode, Dual Parallel Mode and Dual Interleaved ...
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OUTA B7 52 OUTA B7 OUTA B6 53 OUTA B6 OUTA B5 54 OUTA B5 OUTA B4 55 OUTA B4 OUTA B3 56 OUTA B3 OUTA B2 57 OUTA B2 OUTA B1 58 OUTA B1 OUTA B0 59 OUTA B0 ...
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AD9483 Figure 12. Output Latches Section –18– REV. C ...
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REV. C FSADJ IO LO SLEEP FSADJ IO LO SLEEP FSADJ IO LO SLEEP Figure 13. DACs and Clock Buffer Section –19– AD9483 ...
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AD9483 Figure 14. Digital Outputs Connectors and Terminations Section –20– REV. C ...
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Figure 15. Power Connector, Decoupling Capacitors, DC Adjust Variable Resistors Section REV. C –21– AD9483 ...
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AD9483 PCB LAYOUT The PCB is designed on a four layer (1 oz. Cu) board. Compo- nents and routing are on the top layer with a ground flood for additional isolation. Test and ground points were judiciously placed to facilitate ...
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REV. C Figure 16. Layer 1 Routing and Top Layer Ground Figure 17. Layer 2 Ground Plane –23– AD9483 ...
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AD9483 Figure 18. Layer 3 Split Power Planes Figure 19. Layer 4 Routing and Negative 5 V –24– REV. C ...
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... CRCW12061501FT 1.5 kΩ 500 Ω 3296W001501 200 Ω CRCW12062000F Not Installed Not Installed 95F6002 50F3583 Not Installed MC74LCX86D AD9760AR AD9483KS-140/100 MC74LCX574DW AD8055AN Not Installed See Note See Note See Note Supplier Kemit Kemit ITT Cannon Amp Amp Dale Dale ...
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... COMPLIANT TO JEDEC STANDARDS MS-022-GC-1, WITH THE ADDITION OF THE HEATSINK NOTE: THE AD9483KS PACKAGE USES A COPPER INSERT TO HELP DISSIPATE HEAT AND ENSURE RELIABL OPERATION OVER THE FULL +85 C TEMPERATURE RANGE. THIS COPPER INSERT IS EXPOSED ON THE UNDERSIDE OF THE DEVICE RECOMMENDED THAT DURING THE DESIGN OF THE PC BOARD NO THROUGH HOLES OR SIGNAL TRACES BE PLACED UNDER THE AD9483 THAT COULD COME IN CONTACT WIT H THE COPPER INSERT ...
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Revision History Location 11/04—Changed from Rev Rev. C. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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