MCP4651-503E/ST Microchip Technology, MCP4651-503E/ST Datasheet - Page 45

• Manufacturer Part Number: MCP4651-503E/ST
• Description: IC DGTL POT 50K 256TAPS 14-TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP4651-503E/ST

• Package / Case: 14-TSSOP
• Taps: 257
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 50K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 50 KOhms
• Wiper Memory: Volatile
• Digital Interface: Serial (2-Wire, I2C)
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Supply Current: 0.0025 mA (Typ)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.0
The MCP45XX/46XX devices support the I
protocol. The MCP45XX/46XX I
in Slave mode (does not generate the serial clock).
Figure 6-1
I
The MCP45XX/46XX devices use the two-wire I
serial interface. This interface can operate in standard,
fast or High-Speed mode. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions. The MCP45XX/46XX
device works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated. Communi-
cation is initiated by the master (microcontroller) which
sends the START bit, followed by the slave address
byte. The first byte transmitted is always the slave
address byte, which contains the device code, the
address bits, and the R/W bit.
Refer to the Phillips I
the I
FIGURE 6-1:
Diagram.
© 2008 Microchip Technology Inc.
2
C interface signals are high-voltage tolerant.
Typical I
Controller
Note 1: If High voltage commands are desired,
2
Host
C specifications.
I/O
SCL
SDA
2: These pins have internal pull-ups. If
3: This pin could be tied high, low, or
SERIAL INTERFACE (I
shows a typical I
2
(1)
C Interface Connections
some type of external circuitry needs to
be implemented.
faster rise times are required, then
external pull-ups should be added.
connected to an I/O pin of the Host
Controller.
2
C document for more details of
Typical I
2
C Interface connection. All
2
2
C Interface Block
C’s module operates
SCL
SDA
HVC/A0
A1
A2
2
MCP4XXX
C)
(2, 3)
(2, 3)
2
C serial
MCP453X/455X/463X/465X
(2)
2
C
6.1
The I
are:
• SDA (Serial Data)
• SCL (Serial Clock)
• A0 (Address 0 bit)
• A1 (Address 1 bit)
• A2 (Address 2 bit)
6.1.1
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the START and STOP conditions,
the high or low state of the SDA pin can only change
when the clock signal on the SCL pin is low. During the
high period of the clock the SDA pin’s value (high or
low) must be stable. Changes in the SDA pin’s value
while the SCL pin is HIGH will be interpreted as a
START or a STOP condition.
6.1.2
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin. The MCP45XX/46XX supports
three I
• Standard Mode: clock rates up to 100 kHz
• Fast Mode: clock rates up to 400 kHz
• High-Speed Mode (HS mode): clock rates up to
The MCP4XXX will not strech the clock signal (SCL)
since memory read acceses occur fast enough.
Depending on the clock rate mode, the interface will
display different characteristics.
6.1.3
There are up to three hardware pins used to specify the
device address. The number of adress pins is
determined by the part number.
Address 0 is multiplexed with the High Voltage
Command (HVC) function. So the state of A0 is latched
on the MCP4XXX’s POR/BOR event.
The state of the A2 and A1 pins should be static, that is
they should be tied high or tied low.
6.1.3.1
The High Voltage Command (HVC) signal is multi-
plexed with Address 0 (A0) and is used to indicate that
the command, or sequence of commands, are in the
High Voltage mode. High Voltage commands are sup-
ported for compatibility with the non-volatile devices.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal V
3.4 MHz
2
C interface uses up to five pins (signals). These
2
C interface clock modes:
Signal Descriptions
SERIAL DATA (SDA)
SERIAL CLOCK (SCL)
THE ADDRESS BITS (A2:A1:A0)
The High Voltage Command (HVC)
Signal
DD
signal.
DS22096A-page 45