AD5220BRZ10 Analog Devices Inc, AD5220BRZ10 Datasheet - Page 2

• Manufacturer Part Number: AD5220BRZ10
• Description: IC POT DGTL 10K 128POS 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5220BRZ10

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 800 ppm/°C Typical
• Memory Type: Volatile
• Interface: Up/Down Counter
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resistance In Ohms: 10K
• End To End Resistance: 10kohm
• Track Taper: Linear
• No. Of Steps: 128
• Resistance Tolerance: ± 30%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Increment Decrement
• No. Of Pots: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS
Parameter
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
RESISTOR TERMINALS
DIGITAL INPUTS AND OUTPUTS
POWER SUPPLIES
DYNAMIC CHARACTERISTICS
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
NOTES
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
AD5220–SPECIFICATIONS
Typicals represent average readings at +25 C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
INL and DNL are measured at V
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
P
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
All dynamic characteristics use V
See timing diagrams for location of measured values. All input control voltages are specified with t
of 1.6 V. Switching characteristics are measured using both V
DISS
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
Resolution
Integral Nonlinearity
Differential Nonlinearity Error
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
Voltage Range
Capacitance
Capacitance
Common-Mode Leakage
Input Logic High
Input Logic Low
Input Current
Input Capacitance
Power Supply Range
Supply Current
Power Dissipation
Power Supply Sensitivity
Bandwidth –3 dB
Total Harmonic Distortion
V
Resistor Noise Voltage
Input Clock Pulsewidth
CS to CLK Setup Time
CS Rise to Clock Hold Time
U/D to Clock Fall Setup Time
W
is calculated from (I
Settling Time
5
5
A, B
W
4
6
5
3
DD
2
2
V
DD
DD
W
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
= +5 V.
3
5, 7, 8
Symbol
R-DNL
R-INL
R
N
INL
DNL
V
V
V
C
C
I
V
V
I
C
V
I
P
PSS
BW_10K
BW_50K
BW_100K R
THD
t
e
t
t
t
t
S
CH
CSS
CSH
UDS
CM
IL
DD
NWB
R
R
V
DISS
W
WFSE
WZSE
A,
IH
IL
DD
A,
W
IL
DD
AB
W
, t
V
C
/ T
= +5 V.
/ T
CL
B,
B
W
V
(V
otherwise noted)
W
DD
DD
Conditions
R
R
R
R
T
V
I
R
R
R
R
Code = 40
Code = 7F
Code = 00
f = 1 MHz, Measured to GND, Code = 40
f = 1 MHz, Measured to GND, Code = 40
V
V
V
V
V
V
R
R
V
V
10K/50K/100K
R
Clock Level High or Low
= +3 V
= +3 V or +5 V.
W
WB
WB
WB
WB
AB
AB
AB
AB
AB
A
DD
DD
IN
IH
IH
AB
AB
AB
A
A
WB
A
= V
=1 V rms + 2.5 V dc, V
= V
= +25 C
= V
= 0 V or +5 V
= +5 V or V
= +5 V or V
, V
, V
, V
, V
= V
= 10 k
= 50 k , 100 k
= 10 k
= 50 k , 100 k
= 10 k , Code = 40
= 50 k , Code = 40
= 100 k , Code = 40
= +5 V/+3 V
= +5 V/+3 V
= 5 k , f = 1 kHz
DD
A
A
A
A
B
DD
DD
= NC, R
= NC, R
= V
= NC, R
= NC, R
/R, V
, V
5, 9
, Wiper = No Connect
H
H
H
10% or +5 V
B
W
–2–
= 0 V, 50% of Final Value,
DD
IL
IL
AB
AB
AB
AB
= +3 V or +5 V
= 0 V, V
= 0 V, V
= 10 k
= 50 k or 100 k
= 10 k
= 50 k or 100 k
H
H
H
B
DD
DD
= 2.5 V dc, f = 1 kHz
10%, V
R
= +5 V
= +5 V
= t
F
A
= 1 ns (10% to 90% of V
= +V
DD
H
H
, V
B
= 0 V, –40 C < T
Min
–1
–0.5
–1
–0.5
–30
7
–1
–0.5
–1
–0.5
–2
0
0
2.4/2.1
2.7
25
20
20
10
DD
) and timed from a voltage level
A
Typ
800
40
20
–0.5
+0.5
10
48
7.5
5
15
75
0.004
650
142
69
0.002
0.6/3/6
14
= V
0.4
0.1
0.5
0.1
0.5
0.2
0.4
0.1
A
1
DD
< +85 C unless
and V
Max
+1
+0.5
+1
+0.5
+30
100
+1
+0.5
+1
+0.5
0
+1
V
0.8/0.6 V
5.5
40
200
0.015
DD
1
B
= 0 V.
Units
LSB
LSB
LSB
LSB
%
ppm/ C
Bits
LSB
LSB
LSB
LSB
ppm/ C
LSB
LSB
V
pF
pF
nA
V
pF
V
%/%
kHz
kHz
kHz
%
nV/ Hz
ns
ns
ns
ns
REV.
A
A
W
s
A