MCP4351-502E/ML

Manufacturer Part NumberMCP4351-502E/ML
DescriptionIC DGTL POT QUAD 5K 20QFN
ManufacturerMicrochip Technology
MCP4351-502E/ML datasheet
 

Specifications of MCP4351-502E/ML

Taps257Resistance (ohms)5K
Number Of Circuits4Temperature Coefficient150 ppm/°C Typical
Memory TypeVolatileInterfaceSPI Serial
Voltage - Supply1.8 V ~ 5.5 VOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountPackage / Case20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Resistance In Ohms5KLead Free Status / RoHS StatusLead free / RoHS Compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Page 48/88

Download datasheet (6Mb)Embed
PrevNext
MCP433X/435X
6.1
SDI, SDO, SCK, and CS Operation
The operation of the four SPI interface pins are
discussed in this section. These pins are:
• SDI (Serial Data In)
• SDO (Serial Data Out)
• SCK (Serial Clock)
• CS (Chip Select)
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
6.1.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (V
V
), the SDO pin will be driven. The state of the SDO
IHH
pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
6.1.3
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used.
shows the SCK frequency.
TABLE 6-1:
SCK FREQUENCY
Command
Memory Type Access
Read
Volatile
SDI, SDO
10 MHz
Memory
Note 1:
This is the maximum clock frequency
without an external pull-up resistor.
DS22242A-page 48
6.1.4
THE CS SIGNAL
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (V
(V
or V
).
IL
IHH
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (V
error condition, the user must take the CS pin to the V
level.
When the CS pin returns to the inactive state (V
SPI module resets (including the Address Pointer).
While the CS pin is in the inactive state (V
interface is ignored. This allows the host controller to
interface to other SPI devices using the same SDI,
or
SDO and SCK signals.
IL
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the V
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the V
level. When the CS pin is driven low (V
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows High
Voltage
commands.
Table 6-1
commands allows circuit compatibility with the
corresponding nonvolatile device.
(1)
Write,
Increment,
Decrement
10 MHz
) to an active state
IH
). To exit the
IL
IH
) the
IH
), the serial
IH
IL
IH
), the
IL
Support
of
High
Voltage
 2010 Microchip Technology Inc.