DS1844E-010+ Maxim Integrated Products, DS1844E-010+ Datasheet - Page 4

• Manufacturer Part Number: DS1844E-010+
• Description: IC POT DIG QUAD 10K 20-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1844E-010+

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Volatile
• Interface: 2-Wire or 5-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 4 details how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9
bit.
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)
are defined. The DS1844 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1.
2.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will not be released.
The DS1844 may operate in the following two modes:
1.
2.
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master
is the command/control byte. Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The 1
byte) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge
bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
Slave transmitter mode: The 1
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1844 while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer.
st
byte is received and handled as in the slave receiver mode.
4 of 14
st
byte (the command/control
th