MCP4662-502E/UN Microchip Technology, MCP4662-502E/UN Datasheet - Page 68

• Manufacturer Part Number: MCP4662-502E/UN
• Description: IC DGTL POT 5K 256TAPS 10-MSOP
• Manufacturer: Microchip Technology

Specifications of MCP4662-502E/UN

• Taps: 257
• Resistance (ohms): 5K
• Number Of Circuits: 2
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 5K
• End To End Resistance: 5kohm
• Track Taper: Linear
• Resistance Tolerance: ± 20%
• No. Of Steps: 257
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: I2C, Serial
• No. Of Pots: Dual
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP454X/456X/464X/466X
8.2
Figure 8-3
the independent terminals could be used. Disconnect-
ing the wiper allows the transistor input to be taken to
the Bias voltage level (disconnecting A and or B may
be desired to reduce system current). Disconnecting
Terminal A modifies the transistor input by the R
rheostat value to the Common B. Disconnecting
Terminal B modifies the transistor input by the R
rheostat value to the Common A. The Common A and
Common B connections could be connected to V
and V
FIGURE 8-3:
using Terminal Disconnects.
8.3
At times it may become necessary to perform a Soft-
ware Reset Sequence to ensure the MCP45XX/46XX
device is in a correct and known I
This technique only resets the I
This is useful if the MCP45XX/46XX device powers up
in an incorrect state (due to excessive bus noise, ...), or
if the Master Device is reset during communication.
Figure 8-4
ware reset the device.
DS22107A-page 68
Input
Note:
Input
SS
.
Using Shutdown
Software Reset Sequence
shows the communication sequence to soft-
shows a possible application circuit where
Balance
This technique is documented in AN1028.
B
A
Common A
Common B
Example Application Circuit
W
2
Bias
C state machine.
2
C Interface state.
To base
of Transistor
(or Amplifier)
BW
AW
DD
FIGURE 8-4:
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP45XX/46XX is driving an A
bit on the I
command) and is driving a data bit of ‘0’ onto the I
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP45XX/46XX holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A bit (the Master Device does
not drive the I
by the MCP45XX/46XX), which also forces the
MCP45XX/46XX to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP45XX/46XX, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP45XX/46XX is issuing an Acknowledge.
In this case, if the 2nd Start bit is not sent (and the Stop
bit was sent) the MCP45XX/46XX could initiate a write
cycle.
The Stop bit terminates the current I
MCP45XX/46XX wait to detect the next Start condition.
This sequence does not effect any other I
which may be on the bus, as they should disregard this
as an invalid command.
Start
bit
Note:
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
2
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP45XX/46XX.
C bus, or is in output mode (from a Read
2
C bus low to acknowledge the data sent
Nine bits of ‘1’
Software Reset Sequence
© 2008 Microchip Technology Inc.
Stop bit
Start bit
2
C bus activity. The
2
S
C devices
P
2
C