MCP42050-E/SL Microchip Technology, MCP42050-E/SL Datasheet - Page 13

• Manufacturer Part Number: MCP42050-E/SL
• Description: IC POT DGTL 50K 2CH SPI 14SOIC
• Manufacturer: Microchip Technology

Specifications of MCP42050-E/SL

• Temperature Coefficient: 800 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Resistance In Ohms: 50K
• End To End Resistance: 50kohm
• Track Taper: Linear
• No. Of Steps: 256
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, SPI
• No. Of Pots: Dual
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The MCP41XXX/42XXX devices are 256 position
single and dual digital potentiometers that can be used
in place of standard mechanical pots. Resistance val-
ues of 10 k , 50 k
shown in Figure 4-1, each potentiometer is made up of
a variable resistor and an 8-bit (256 position) data reg-
ister that determines the wiper position. There is a
nominal wiper resistance of 52 for the 10 k version,
125
devices, the channel-to-channel matching variation is
less than 1%. The resistance between the wiper and
either of the resistor endpoints varies linearly according
to the value stored in the data register. Code 00h
effectively connects the wiper to the B terminal. At
FIGURE 4-1:
data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with
the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and
wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B,
without changing the state of the data registers.
2003 Microchip Technology Inc.
for the 50 k
µC
APPLICATIONS INFORMATION
V
DD
Data Lines
RS
CS
and 100 k
Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and
and 100 k
0.1 uF
versions. For the dual
SCK
are available. As
V
To Application
DD
B
W
A
Circuit
PA0
Data Register 0
0.1 uF
D7
RDAC1
PW0
SI
Decode
Logic
16-bit Shift Register
power-up, all data registers will automatically be loaded
with the mid-scale value (80h). The serial interface pro-
vides the means for loading data into the shift register,
which is then transferred to the data registers. The
serial interface also provides the means to place indi-
vidual potentiometers in the shutdown mode for maxi-
mum power savings. The SHDN pin can also be used
to put all potentiometers in shutdown mode and the RS
pin is provided to set all potentiometers to mid-scale
(80h).
When laying out the circuit for your digital potentiome-
ter, bypass capacitors should be used. These capaci-
tors should be placed as close as possible to the device
pin. A bypass capacitor value of 0.1 µF is recom-
mended. Digital and analog traces should be separated
as much as possible on the board, with no traces run-
ning underneath the device or the bypass capacitor.
Extra precautions should be taken to keep traces with
high-frequency signals (such as clock lines) as far as
possible from analog traces. Use of an analog ground
plane is recommended in order to keep the ground
potential the same for all devices on the board.
PB0
D0
PA1
D7
MCP41XXX/42XXX
Data Register 1
RDAC2
D7
PW1
SO
D0
PB1
D0
SHDN
DS11195C-page 13