AD5170BRM100-RL7 Analog Devices Inc, AD5170BRM100-RL7 Datasheet - Page 16

• Manufacturer Part Number: AD5170BRM100-RL7
• Description: IC DGTL POT 100K 256POS 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5170BRM100-RL7

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K

AD5170
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as shown
in Figure 37 and Figure 38.
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 V
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed V
forward-biased diodes (see Figure 39).
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W, it is important to
power V
Terminal B, and Terminal W (see Figure 39). Otherwise, the
diode is forward-biased such that V
and may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, V
The relative order of powering V
is not important as long as they are powered up after GND/V
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies share the
same V
link technology that requires 5.6 V to 5.8 V for blowing the
internal fuses to achieve a given setting, but normal V
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are needed if
system V
ming supply (either an on-board regulator or rack-mount power
supply) must be rated at 5.6 V to 5.8 V and be able to provide a
100 mA current for 400 ms for successful OTP.
Figure 39. Maximum Terminal Voltages Set by V
DD
DD
DD
terminal of the AD5170. The AD5170 employs fuse
/GND before applying any voltage to Terminal A,
is lower than the required V
Figure 38. ESD Protection of Resistor Terminals
DD
Figure 37. ESD Protection of Digital Pins
-to-GND power supply defines the boundary
DD
, the digital inputs, and then V
A, B, W
GND
GND
DD
340Ω
or GND are clamped by the internal
A
LOGIC
, V
DD
B
is powered unintentionally
, V
DD_OTP
W
, and the digital inputs
V
A
W
B
GND
DD
. The fuse program-
DD
and GND
A
DD
/V
B
can be
/V
W
Rev. F | Page 16 of 24
.
DD
.
When the fuse programming is complete, the V
must be removed to allow normal operation at 2.7 V to 5.5 V,
and the device consumes current in the μA range.
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-Channel MOSFETs is recom-
mended for the isolation of the supply. As shown in Figure 40,
this assumes that the 2.7 V system voltage is applied first, and
the P1 and P2 gates are pulled to ground, thus turning on P1 and,
subsequently, P2. As a result, V
When the AD5170 setting is found, the factory tester applies the
V
and P2. The OTP command is executed at this time to program the
AD5170 while the 2.7 V source is protected. When the fuse pro-
gramming is complete, the tester withdraws the V
setting for the AD5170 is permanently fixed.
The AD5170 achieves the OTP function by blowing internal
fuses. Users should always apply the 5.6 V to 5.8 V one-time-
program voltage requirement at the first fuse programming
attempt. Failure to comply with this requirement can lead to a
change in the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × V
Shifting for Different Voltage Operation section.
Poor PCB layout introduces parasitics that can affect the fuse
programming. Therefore, it is recommended to add a 10 μF
tantalum capacitor in parallel with a 1 nF ceramic capacitor as
close as possible to the V
both capacitors are important. This combination of capacitor
values provides both a fast response and larger supply current
handling with minimum supply droop during transients. As a
result, these capacitors increase the OTP programming success
by not inhibiting the proper energy needed to blow the internal
fuses. Additionally, C1 minimizes transient disturbance and low
frequency ripple, and C2 reduces high frequency noise during
normal operation.
DD_OTP
5.7V
2.7V
Figure 40. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
to both the V
10kΩ
R1
P1 = P2 = FDV302P, NDS0610
P1
APPLY FOR OTP ONLY
P2
DD
and the MOSFETs gates, turning off P1
DD
10µF
DD
C1
pin. The type and value chosen for
and V
DD
0.1µF
of the AD5170 approaches 2.7 V.
C2
DD
+ 0.5 V. Refer to the Level
V
DD
AD5170
DD_OTP
DD_OTP
supply
and the