IC POT DIG QUAD 1K 8BIT 24TSSOP

AD8403ARU1-REEL

Manufacturer Part NumberAD8403ARU1-REEL
DescriptionIC POT DIG QUAD 1K 8BIT 24TSSOP
ManufacturerAnalog Devices Inc
AD8403ARU1-REEL datasheet
 


Specifications of AD8403ARU1-REEL

Rohs StatusRoHS non-compliantTaps256
Resistance (ohms)1KNumber Of Circuits4
Temperature Coefficient500 ppm/°C TypicalMemory TypeVolatile
InterfaceSPI, 3-Wire SerialVoltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case24-TSSOPResistance In Ohms1.00K
For Use WithAD8403EVAL - BOARD EVAL FOR AD8403  
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Like a mechanical potentiometer, RDAC is symmetrical. The
resistance between the Wiper W and Terminal A also produces
a digitally controlled complementary resistance, R
these terminals are used, the B terminal can be tied to the wiper
or left floating. R
starts at the maximum and decreases as the
WA
data loaded into the RDAC latch increases. The general transfer
equation for this R
is
WA
( )
256
D
=
×
+
R
D
R
R
WA
AB
W
256
where D is the data loaded into the 8-bit RDAC# latch, and R
is the nominal end-to-end resistance.
For example, when the B terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following R
(for the 10 kΩ version):
WA
Table 11.
D (Dec)
R
(Ω)
Output State
WA
255
89
Full-Scale
128
5,050
Midscale ( RS = 0 Condition)
1
10,011
1 LSB
0
10,050
Zero-Scale
The typical distribution of RAB from channel to channel
matches within ±1%. However, device-to-device matching
is process lot dependent and has a ±20% variation. The tem-
perature coefficient, or the change in R
AB
is 500 ppm/°C.
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not con-
tribute any significant temperature related errors. The graph in
Figure 18 shows the performance of R
WB
the potentiometer with codes below 32 results in the larger
temperature coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting the A terminal to 5 V and the B termi-
nal to ground produces an output voltage at the wiper starting
at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage
applied across the A to B terminals divided by the 256-position
resolution of the potentiometer divider. The general equation
defining the output voltage with respect to ground for any given
input voltage applied to the A to B terminals is
D
=
×
+
V
V
V
W
AB
B
256
Operation of the digital potentiometer in the voltage divider
mode results in more accurate operation over temperature.
Here the output voltage is dependent on the ratio of the internal
resistors, not the absolute value; therefore, the temperature drift
. When
improves to 15 ppm/°C.
WA
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases because the contribution of
the CMOS switch wiper resistance becomes an appreciable
portion of the total resistance from the B terminal to the
Wiper W. See Figure 17 for a plot of potentiometer tempco
(3)
performance vs. code setting.
DIGITAL INTERFACING
AB
The AD8400/AD8402/AD8403 contain a standard SPI-
compatible, 3-wire, serial input control interface. The three
inputs are clock (CLK), chip select ( CS ), and serial data input
(SDI). The positive-edge sensitive CLK input requires clean
transitions to avoid clocking incorrect data into the serial input
register. For the best result, use logic transitions faster than
1 V/μs. Standard logic families work well. If mechanical switches
are used for product evaluation, they should be debounced by
a flip-flop or other suitable means. The block diagrams in
Figure 46 Figure 47
circuitry in more detail. When
loads data into the 10-bit serial register on each positive clock
edge (see
with temperature,
tempco vs. code. Using
(4)
Rev. E | Page 21 of 32
AD8400/AD8402/AD8403
,
, and
Figure 48
show the internal digital
CS is taken active low, the clock
Table 12
).
CS
CLK
D7
EN
RDAC
LATCH
NO. 1
ADDR
A1
D0
DEC
A0
D7
10-BIT
SER
AD8400
REG
SDI
DI D0
8
GND
Figure 46. AD8400 Block Diagram
AD8402
CS
CLK
D7
RDAC
EN
LATCH
NO. 1
ADDR
R
D0
A1
DEC
A0
D7
10-BIT
D7
SER
RDAC
REG
LATCH
NO. 2
SDI
DI
D0
R
D0
8
SHDN
DGND
AGND
RS
Figure 47. AD8402 Block Diagram
V
DD
A1
W1
B1
V DD
A1
W1
B1
A4
W4
B4