DS1859E-050 Maxim Integrated Products, DS1859E-050 Datasheet - Page 26

• Manufacturer Part Number: DS1859E-050
• Description: IC RES TEMP 50/50K 3MON 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1859E-050

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.85 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Figure 6. 2-Wire AC Characteristics
operation, incremented by one. This data is maintained
as long as V
the last byte in memory, then the register resets to the
first address.
Once the device address is clocked in and acknowl-
edged by the DS1859 with the R/W bit set to high, the
current address data word is clocked out. The master
does not respond with a zero, but does generate a
STOP condition afterwards.
A random read requires a dummy byte write sequence to
load in the data byte address. Once the device and data
address bytes are clocked in by the master and acknowl-
edged by the DS1859, the master must generate another
START condition. The master now initiates a current
address read by sending the device address with the
R/W bit set high. The DS1859 acknowledges the device
address and serially clocks out the data byte.
Sequential reads are initiated by either a current
address read or a random address read. After the mas-
ter receives the first data byte, the master responds
with an acknowledge. As long as the DS1859 receives
this acknowledge after a byte is read, the master can
clock out additional data words from the DS1859. After
reaching address FFh, it resets to address 00h.
26
SDA
SCL
____________________________________________________________________
STOP
CC
t
BUF
is valid. If the most recent address was
START
t
HD:STA
t
LOW
Sequential Address Read
t
R
t
HD:DAT
Single Read
t
F
t
HIGH
t
SU:DAT
The sequential read operation is terminated when the
master initiates a STOP condition. The master does not
respond with a zero.
The following section provides a detailed description of
the 2-wire theory of operation.
The 2-wire serial-port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device that receives data as a receiver.
The device that controls the message is called a mas-
ter. The devices that are controlled by the master are
slaves. The bus must be controlled by a master device
that generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions. The DS1859 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL. The following I/O
terminals control the 2-wire serial port: SDA, SCL.
Timing diagrams for the 2-wire serial port can be found
in Figures 5 and 6. Timing information for the 2-wire
serial port is provided in the AC Electrical
Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
◆
◆
REPEATED
START
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
t
2-Wire Serial-Port Operation
SU:STA
t
HD:STA
t
SP
t
SU:STO