CS4353-CNZ Cirrus Logic Inc, CS4353-CNZ Datasheet
CS4353-CNZ
Specifications of CS4353-CNZ
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CS4353-CNZ Summary of contents
Page 1
... Full-scale Output The CS4353 is available in a 24-pin QFN package in Commercial (-40°C to +85°C) grade. The CDB4353 Customer Demonstration Board is also available for de- vice evaluation and implementation suggestions. ...
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... Internal Power-on Reset Power-up Sequence .......................................................... 19 4.9.2 Power-down Sequences ....................................................................................................... 19 4.9.2.1 External RESET Power-down Sequence .................................................................. 19 4.9.2.2 Internal Power-on Reset Power-down Sequence ...................................................... 19 4.10.1 Capacitor Placement ........................................................................................................... 20 5. DIGITAL FILTER RESPONSE PLOTS ................................................................................................ 21 6. PARAMETER DEFINITIONS ................................................................................................................ 23 7. PACKAGE DIMENSIONS .................................................................................................................... 24 8. ORDERING INFORMATION ................................................................................................................ 25 9. REVISION HISTORY ............................................................................................................................ 25 2 CS4353 DS803F1 ...
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... Figure 19.Quad-speed Transition Band .................................................................................................... 22 Figure 20.Quad-speed Transition Band (detail) ........................................................................................ 22 Figure 21.Quad-speed Passband Ripple .................................................................................................. 22 LIST OF TABLES Table 1. Digital I/O Pin Characteristics ..................................................................................................... 11 Table 2. CS4353 Operational Mode Auto-Detect ...................................................................................... 14 Table 3. Single-speed Mode Standard Frequencies ................................................................................. 14 Table 4. Double-speed Mode Standard Frequencies ............................................................................... 14 Table 5. Quad-speed Mode Standard Frequencies .................................................................................. 14 Table 6. Digital Interface Format ............................................................................................................... 15 ...
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... This pin must be at the same nominal DC voltage as the AGND pin. AGND 16 Analog Ground (Input) - Ground reference for the low voltage analog section Thermal Pad 4 5 Top-Down (Through Package) View 24-Pin QFN Package Pin Description CS4353 19 VBIAS AGND 16 AOUTA 15 AOUT_REF 14 13 AOUTB 12 DS803F1 ...
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... Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated Thermal Pad - from all board connections. DS803F1 threshold (see off 10.). This pin should be set high (VL) during nor- . RMS CS4353 See 5 ...
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... Interface power Symbol VCP Low Voltage Analog Power VA Supply Voltage Difference |VCP - VA| Interface Power Digital Interface V IN-L AOUT_REF V IN stg CS4353 Min Typ Max Units 3.13 3.3 3.47 V 3.13 3.3 3.47 V 0.85 0.9 to 3.3 3.47 V -40 - +85 °C Min Max Units -0.3 3 ...
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... OUTmax - 0.1 - ±5 - 100 Z - 100 OUT (Notes 8, 9) AOR - 40 (Note 10 specification valid for sine wave signals only. RMS --------- - RMS 2 2 CS4353 Figure 3 on page 12; input test signal is a 1_2VRMS = 1 Max Min Typ Max - 100 106 - - 97 103 - - - -87 - -93 -87 -71 - -83 -77 -31 - -43 ...
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... AOR = 20 log AOUT_REF AOUTx – to -0.01 dB corner corner (Note 12 44.1 kHz to -0.01 dB corner corner (Note 12) to -0.01 dB corner corner (Note 12) to -0.05 dB corner 9.00x10 corner 9.74x10 CS4353 Min Typ Max 0 - .454 0 - .499 -0.01 - +0.01 0.547 - - 102 - - - 9.4/Fs ...
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... SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time ATA DS803F1 Symbol Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode t slrs t slrd t sclkl sdlrs Figure 1. Serial Input Timing CS4353 Min Max 2.048 51 108 Fs 170 216 sclkl t 20 ...
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... DGND reset (internal reset No Power undefined 10 Symbol 1.2 V < VL ≤ 3.3 V 0.9 V ≤ VL ≤ 1.2 V 1.2 V < VL ≤ 3.3 V 0.9 V ≤ VL ≤ 1.2 V Symbol DAC reset Ready active Figure 2. Power-on Reset Threshold Sequence CS4353 Min Typ Max V 0.7xVL - - IH V 0.9xVL - - 0.3xVL IL V ...
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... FLYN+ to FLYN- GND to VFILT- (Note 18 VBIAS Switching Specifications - Serial Audio Section 4.8. Typical voltage may 1.5 V lower I/O Driver Input - Input - Input - Input - Input - Input - Input - Input - Table 1. Digital I/O Pin Characteristics CS4353 Min Typ Max Units - 2 0.1 0.2 mA μ 127 152 mW - ...
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... RESET 19 FLYN+ 9 I²S/LJ 22 FLYN- 11 DEM 21 VFILT- 12 1_2VRMS Figure 3. Typical Connection Diagram CS4353 + 2.2 µF + 0.1 µF 2.2 µF + 2.2 µF Line Level Out Left & Right 562 Ω 2.2 nF 2.2 nF 562 Ω Note 1 + Note 1: Values shown are for 2.2 µ 130 kHz ...
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... An on-chip charge pump creates both positive and negative high-voltage supplies, which allows the full- scale output swing to be centered around ground. This eliminates the need for large DC-blocking capac- itors which create audible pops at power-on, allows the CS4353 to deliver a larger full-scale output at low- er supply voltages, and provides improved bandwidth frequency response. ...
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... Sample Rate Range/Operational Mode Detect The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 2. Sample rates outside the specified range for each mode are not supported. In addition to a valid LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device for speed mode auto-detection ...
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... For all formats, SDIN is valid on the rising edge of SCLK. Also, Description I² 24-bit Data Left-Justified 24-bit Data Table 6. Digital Interface Format + LSB M SB Figure 5. I² 24-bit Data + LSB M SB Figure 6. Left-justified up to 24-bit Data CS4353 Figure LSB table for filter specifications. 15 ...
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... Internal Power-on Reset The CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be connected to VL during power-up and power-down sequences if the external reset function is not needed. This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches defined thresholds (see ages” ...
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... If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RE- SET being set high to the analog audio output from AOUTx is less than 50 ms. See Figure 9 for a diagram of the device’s states and transition conditions. DS803F1 CS4353 17 ...
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... Power-Down State USER: Apply MCLK Initialization State USER: Apply LRCK and SCLK MCLK/LRCK Ratio Detection Valid MCLK/LRCK Ratio Power-Up State Outputs Muted Normal Operation State Analog Output Generated USER: Change MCLK/LRCK ratio Mute State CS4353 USER: RESET Set Low or Remove MCLK DS803F1 ...
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... MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see DS803F1 4.3. Figure Section 4.7. “Switching Specifications - Serial Audio Interface” on page CS4353 9. The sequence will complete and audio Figure ...
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... CS4353. All signals, especially clocks, should be kept away from the VBIAS pin in order to avoid unwanted coupling into the DAC ...
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... Figure 13. Single-speed Passband Ripple 100 120 0.4 0.42 0.8 0.9 1 Figure 15. Double-speed Transition Band CS4353 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 ...
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... Figure 19. Quad-speed Transition Band 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 0 0.52 0.53 0.54 0.55 Figure 21. Quad-speed Passband Ripple CS4353 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 ...
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... Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS803F1 CS4353 23 ...
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... Controlling Dimension is Millimeters Symbol θ 2 Layer Board JA θ 4 Layer Board JA CS4353 b e PIN #1 CORNER D2 L BOTTOM VIEW NOTE MILLIMETERS NOM MAX - 1. 0.05 1 0.25 0.30 1, 0.50 0.55 1 4.00 BSC 1 2 ...
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... DAC Analog Characteristics Internal Power-on Reset Threshold Voltages Filter. CS4353 Temp Range Container Order # Rail CS4353-CNZ -40° to +85° C Tape & Reel CS4353-CNZR - - CDB4353 specification table. DC Electrical Characteristics table. table. specification table. DAC Analog Characteristics table. table. table. table. table. ...
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... TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 26 CS4353 DS803F1 ...