CS4365-CQZ Cirrus Logic Inc, CS4365-CQZ Datasheet
CS4365-CQZ
Specifications of CS4365-CQZ
Available stocks
Related parts for CS4365-CQZ
CS4365-CQZ Summary of contents
Page 1
... It also offers an optional path for direct DSD conversion by di- rectly using the multi-element switched capacitor array. The CS4365 is available in a 48-pin LQFP package in both Commercial (-40°C to +85°C) and Automotive (-40°C to +105°C) grades. The CDB4365 Customer Demonstration board is also available for device evalu- ation and implementation suggestions ...
Page 2
... INCR (Auto Map Increment Enable) .................................................................................... 32 4.15.2 MAP4-0 (Memory Address Pointer) .................................................................................... 32 5. REGISTER QUICK REFERENCE ....................................................................................................... 33 6. REGISTER DESCRIPTION .................................................................................................................. 34 6.1 Chip Revision (address 01h) ......................................................................................................... 34 6.1.1 Part Number ID (PART) [Read Only] .................................................................................... 34 6.2 Mode Control 1 (address 02h) ........................................................................................................ 34 6.2.1 Control Port Enable (CPEN) .................................................................................................. 34 6.2.2 Freeze Controls (FREEZE) ................................................................................................... 34 2 CS4365 DS670F2 ...
Page 3
... Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h) ............................................................ 43 6.11.1 Digital Volume Control (xx_VOL7:0) ................................................................................... 43 6.12 PCM Clock Mode (address 16h) .................................................................................................. 44 6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV) ................................................................ 44 7. FILTER PLOTS ..................................................................................................................................... 45 8. PARAMETER DEFINITIONS ................................................................................................................ 49 9. PACKAGE DIMENSIONS ................................................................................................................... 50 10. ORDERING INFORMATION .............................................................................................................. 51 11. REFERENCES .................................................................................................................................... 51 12. REVISION HISTORY ......................................................................................................................... 51 DS670F2 CS4365 3 ...
Page 4
... Figure 40.Quad-Speed (fast) Stopband Rejection .................................................................................... 47 Figure 41.Quad-Speed (fast) Transition Band .......................................................................................... 47 Figure 42.Quad-Speed (fast) Transition Band (detail) .............................................................................. 48 Figure 43.Quad-Speed (fast) Passband Ripple ........................................................................................ 48 Figure 44.Quad-Speed (slow) Stopband Rejection ................................................................................... 48 Figure 45.Quad-Speed (slow) Transition Band ......................................................................................... 48 Figure 46.Quad-Speed (slow) Transition Band (detail) ............................................................................. 48 Figure 47.Quad-Speed (slow) Passband Ripple ....................................................................................... 48 4 CS4365 DS670F2 ...
Page 5
... Table 4. PCM Digital Interface Format, Hardware Mode Options ............................................................. 22 Table 5. Mode Selection, Hardware Mode Options .................................................................................. 22 Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 22 Table 7. Digital Interface Formats - PCM Mode ........................................................................................ 36 Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 36 Table 9. ATAPI Decode Table .................................................................................................................. 42 Table 10. Example Digital Volume Settings .............................................................................................. 43 DS670F2 CS4365 5 ...
Page 6
... DSDA1 GND 5 6 MCLK CS4365 LRCK 7 SDIN1 8 SCLK 9 10 M4(TST) SDIN2 11 M3(TST Pin Description 3 illustrate several standard audio sample rates and the required master clock fre- CS4365 36 AOUTA2- 35 AOUTA2+ 34 AOUTB2+ 33 AOUTB2 GND 31 30 AOUTA3- 29 AOUTA3+ 28 AOUTB3+ 27 AOUTB3- 26 MUTEC2 25 MUTEC3 Tables 1 DS670F2 ...
Page 7
... Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. GND if DSDB2 48 unused. DSDA3 47 DSDB3 46 DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface. DS670F2 Pin Description 7. CS4365 Table 6 ® Mode as shown in the Typical Connection ™ Mode. 7 ...
Page 8
... Analog power VA Digital internal power VD VLS Control port interface power VLC Any Pin Except Supplies I in Serial data port interface V IND-S Control port interface V IND stg CS4365 Min Typ Max 4.75 5.0 5.25 2.37 2.5 2.63 1.71 5.0 5.25 1.71 5.0 5.25 - ...
Page 9
... THD+N 16-bit 0 dB -20 dB -60 dB A-weighted (1 kHz) PCM, DSD processor 1.28• Direct DSD Mode 0.90•V Z OUT I OUTmax QMAX and includes attenuation due CS4365 = 25°C; Full-scale 997 Hz A Min Typ Max 108 114 - 105 111 - - -100 - -51 -45 - -94 ...
Page 10
... THD+N 16-bit 0 dB -20 dB -60 dB A-weighted (1 kHz) PCM, DSD processor 1.28• Direct DSD Mode 0.90•V Z OUT I OUTmax QMAX CS4365 ; Tested under max ac-load (Note 1) ; Measure- Typ Max Units 114 - 111 - - -100 - -51 -42 - -94 - ...
Page 11
... Valid with the recommended capacitor values on FILT+ and VQ as shown in DS670F2 Symbol normal operation, VA VD= 2 Interface current, VLC VLS power-down state (all supplies 2.5 V normal operation (Note 6) power-down θ multi-layer JA θ dual-layer JA θ kHz) PSRR (60 Hz) CS4365 Min Typ Max Units - μ μ μA - 200 - - 340 390 ...
Page 12
... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .583 (Note 10 6.15/Fs to -0.01 dB corner corner kHz -0.01 .635 (Note 10 7.1/Fs Section 7. “Filter Plots” on page CS4365 Unit Typ Max - .454 Fs - .499 Fs - +0. ±0. ±0. ±0. .430 Fs - .499 ...
Page 13
... Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .792 (Note 10 5.4/Fs to -0.01 dB corner corner kHz -0.01 .868 (Note 10 6.6/Fs Min corner kHz -0. -0.1 dB corner corner 0 -0.1 CS4365 (Note 8) Unit Typ Max - 0.417 Fs - 0.499 Fs - +0. ±0. ±0. ±0. .296 Fs - .499 Fs - +0.01 ...
Page 14
... Any pin except supplies. Transient currents ±100 mA on the input pins will not cause SCR latch- up. 14 Symbol (Note 13 Serial I/O V 0.70•V IH Control I/O V 0.70•V IH Serial I Control I Control I 0.70• max CS4365 Min Typ Max Units μ ± 0.30• 0.30• 0.20• 0.25• ...
Page 15
... MSB of CH1 is always the second SCLK rising edge following LRCK rising edge. LRCK SCLK SDINx DS670F2 = 20 pF. L (Note 14) (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode lcks sckh sckl MSB Figure 1. Serial Audio Interface Timing CS4365 Symbol Min Max 1 - 1.024 55 108 s F 100 216 ...
Page 16
... DSD_SCLK (64Fs) DSDxx Figure 3. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode Symbol t sclkl t sclkh (64x Oversampled) (128x Oversampled) t sdlrs t sdh t dpm t t sdlrs sdh t t dpm dpm CS4365 Min Typ Max 160 - - 160 - - 1.024 - 3.2 2.048 - 6 - ...
Page 17
... Repeated t high t t sud t sust hdd Figure 4. Control Port Timing - I²C Format CS4365 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop Start ...
Page 18
... L Symbol f sclk t srs (Note 18) t spi t csh t css t scl t sch t dsu (Note 19 (Note 20 (Note 20 css t scl t sch dsu t dh Figure 5. Control Port Timing - SPI Format CS4365 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
Page 19
... RST MUTEC5 15 SCL/CCLK MUTEC6 16 SDA/CDIN 17 ADO/CS Note* FILT+ 18 VLC CMOUT 0.1 µF GND TST GND 10, 12 14, 44, 45 CS4365 + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 Analog Conditioning 30 and Muting ...
Page 20
... KΩ AOUTB3 AOUTB3 MUTEC6 RST FILT+ CMOUT 18 VLC 0.1 µF GND TST GND 5 31 14, 44, 45 CS4365 + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 41 38 Analog Conditioning 37 and Muting 26 35 Analog Conditioning 36 and Muting 25 34 Analog Conditioning 33 and Muting 24 29 Analog Conditioning ...
Page 21
... SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces, see Cirrus Application Note AN282, “The 2-Channel Serial Audio Interface: A Tutorial.” The CS4365 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode through I²C or SPI. ...
Page 22
... DSD data with a 2x MCLK to DSD data rate 0 128x oversampled DSD data with a 3x MCLK to DSD data rate 1 128x oversampled DSD data with a 4x MCLK to DSD data rate 0 128x oversampled DSD data with a 6x MCLK to DSD data rate 1 CS4365 FORMAT FIGURE DESCRIPTION ...
Page 23
... Left Channel SCLK SDINx Figure 12. Format 4 - Right-Justified 20-bit Data DS670F2 Left Channel + LSB MSB Left Channel + LSB MSB Figure 9. Format 1 - I² 24-bit Data clocks CS4365 Figures 8-15. Data is Right Channel - LSB Right Channel - LSB Right Channel Right Channel Right Channel ...
Page 24
... The auto-speed mode detect feature allows for the automatic selection of speed mode based off of the in- coming sample rate. This allows the CS4365 to accept a wide range of sample rates with no external inter- vention necessary. The auto-speed mode detect feature is available in both hardware and Software Mode. ...
Page 25
... Filter specifications can be found in 4.6 De-Emphasis The CS4365 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommo- date older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate the input sample rate does not match the coefficient which has been se- lected ...
Page 26
... CS4365, but may lower the sensitivity to board-level routing of the DSD data signals. The CS4365 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4365 to alter the incoming invalid DSD data. ...
Page 27
... The Typical Connection Diagram shows the rec- ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4365 should be connect the analog ground plane. ...
Page 28
... Analog Output and Filtering The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4365 evalua- tion board, CDB4365, as seen in tion for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry ...
Page 29
... The external mute circuitry needs to be self-biased into an active state in order to be muted during reset. Upon release of reset, the CS4365 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The external-bias voltage level that the MUTEC pins see at the time of release of reset must meet the “ ...
Page 30
... If the device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected. 30 Section 4.1. In this state, the registers are reset to the default 45). The operation of the control port may be completely asynchronous with Figure 22 for the clock to data relationship). There pin. The AD0 pin CS4365 DS670F2 ...
Page 31
... DS670F2 4.14.1) is set to 1, repeat the previous step until all the desired registers Section 4.14. I²C read is the first operation performed on the N ote 1 ADDR DATA R/W ACK ACK AD 0 1-8 Figure 22. Control Port Timing, I²C Mode CS4365 DATA ACK 1-8 Stop 31 ...
Page 32
... Default = ‘00000’ 32 4.14.1) is set to 1, repeat the previous step until all the desired registers CHIP MAP ADDRESS 0011000 R/W MSB byte ory Address Pointer Figure 23. Control Port Timing, SPI Mode MAP4 MAP3 CS4365 DATA LSB byte MAP2 MAP1 MAP0 DS670F2 ...
Page 33
... P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 A2_VOL6 A2_VOL5 A2_VOL4 B2_VOL6 B2_VOL5 B2_VOL4 P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 A3_VOL6 A3_VOL5 A3_VOL4 B3_VOL6 B3_VOL5 B3_VOL4 Reserved MCLKDIV Reserved CS4365 PART0 REV REV Reserved Reserved FM1 INVALID_D DSD_PM_ DSD_PM_ Reserved Reserved Reserved INV_B2 INV_A2 INV_B1 P2_A=B ...
Page 34
... Chip Revision (address 01h PART4 PART3 PART2 0 1 6.1.1 Part Number ID (PART) [Read Only] 01101- CS4365 Revision ID (REV) [Read Only] 000 - Revision A0 001 - Revision B0 Function: This read-only register can be used to identify the model and revision number of the device. 6.2 Mode Control 1 (address 02h) 7 ...
Page 35
... The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set to ensure proper switching from one mode to another. DS670F2 DIF0 Reserved Figures 8 through 15. CS4365 Reserved FM1 FM0 ...
Page 36
... DSD data with a 2x MCLK to DSD data rate 1 128x oversampled DSD data with a 3x MCLK to DSD data rate 0 128x oversampled DSD data with a 4x MCLK to DSD data rate 1 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 8. Digital Interface Formats - DSD Mode CS4365 FORMAT ...
Page 37
... When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode. 6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) Function: When set to 1, DSD phase modulation input mode is enabled, and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode). DS670F2 27) CS4365 Section ), the dynamic range 37 ...
Page 38
... AOUT1A and AOUT1B on MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3 Reserved Reserved INV_A3 INV_B2 P1_A=B P2_A CS4365 Reserved Reserved FILT_SEL INV_A2 INV_B1 INV_A1 P3_A=B Reserved SNGLVOL 0 0 ...
Page 39
... The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate per 8 left/right clock periods. DS670F2 RMP_DN PAMUTE CS4365 DAMUTE MUTE_P1 MUTE_P0 ...
Page 40
... A single sample of non-static data will release the mute. De- tection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0, this function is disabled. 40 CS4365 DS670F2 ...
Page 41
... The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bits. DS670F2 for description MUTE_A3 MUTE_B2 CS4365 MUTE_A2 MUTE_B1 MUTE_A1 ...
Page 42
... De-emphasis is only available in Single-Speed Mode. 6.10.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4365 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 ...
Page 43
... Table 9. ATAPI Decode Table xx_VOL4 xx_VOL3 Table 10 are approximate. The actual attenuation is determined Decimal Value 00000000 0 00000001 1 00000110 6 11111111 255 Table 10. Example Digital Volume Settings CS4365 AOUTAx AOUTBx MUTE [(bL+aR)/2] aR MUTE [(aL+bR)/2] aL MUTE [(aL+bR)/2] [(aL+bR)/2] MUTE [(aL+bR)/2] bR [(bL+aR)/2] ...
Page 44
... Master Clock DIVIDE by 2 ENABLE (MCLKDIV) Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged Reserved Reserved CS4365 Reserved Reserved Reserved DS670F2 ...
Page 45
... Figure 27. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 29. Single-Speed (slow) Transition Band CS4365 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0 ...
Page 46
... Figure 33. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 35. Double-Speed (fast) Passband Ripple CS4365 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...
Page 47
... Figure 39. Double-Speed (slow) Passband Ripple 100 120 0.7 0.8 0.9 1 0.2 Figure 41. Quad-Speed (fast) Transition Band CS4365 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...
Page 48
... Figure 45. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 47. Quad-Speed (slow) Passband Ripple CS4365 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 ...
Page 49
... Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS670F2 CS4365 49 ...
Page 50
... Nominal pin pitch is 0.50 mm *Controlling dimension is mm. *JEDEC Designation: MS022 CS4365 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9 ...
Page 51
... LQFP Automotive -40°C to +105° Changes “Recommended Operating Conditions” on page page 52 “Mode Select” on page 22 “Power and Thermal Characteristics” on page 11 CS4365 Temp Range Container Order # Tray CS4365-CQZ Tape & Reel CS4365-CQZR Tray CS4365-DQZ Tape & Reel CS4365-DQZR - - CDB4365 8. 51 ...
Page 52
... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 52 www.cirrus.com CS4365 DS670F2 ...