CS4384-CQZ Cirrus Logic Inc, CS4384-CQZ Datasheet
CS4384-CQZ
Specifications of CS4384-CQZ
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CS4384-CQZ Summary of contents
Page 1
... DSD conversion by di- rectly using the multi-element switched capacitor array. The CS4384 accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excel- lent sound quality. These features are ideal for multi- ...
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... MAP4-0 (Memory Address Pointer) ................................................................................... 32 5. REGISTER QUICK REFERENCE ....................................................................................................... 33 6. REGISTER DESCRIPTION .................................................................................................................. 35 6.1 Chip Revision (Address 01h) ......................................................................................................... 35 6.1.1 Part Number ID (PART) [Read Only] ................................................................................... 35 6.1.2 Revision ID (REV) [Read Only] ............................................................................................ 35 6.2 Mode Control 1 (Address 02h) ...................................................................................................... 35 6.2.1 Control Port Enable (CPEN) ................................................................................................ 35 6.2.2 Freeze Controls (FREEZE) .................................................................................................. 35 2 ................................................................................................ 18 CS4384 DS620F1 ...
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... Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)........................................... 44 6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 44 6.12 PCM Clock Mode (Address 16h) ................................................................................................. 44 6.12.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 44 7. FILTER RESPONSE PLOTS ............................................................................................................... 45 8. REFERENCES...................................................................................................................................... 49 9. PARAMETER DEFINITIONS................................................................................................................ 49 10. PACKAGE DIMENSIONS .................................................................................................................. 50 11. ORDERING INFORMATION .............................................................................................................. 51 12. REVISION HISTORY ......................................................................................................................... 51 DS620F1 CS4384 3 ...
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... Figure 44. Quad-Speed (fast) Stopband Rejection .................................................................................... 47 Figure 45. Quad-Speed (fast) Transition Band .......................................................................................... 47 Figure 46. Quad-Speed (fast) Transition Band (detail) .............................................................................. 48 Figure 47. Quad-Speed (fast) Passband Ripple ........................................................................................ 48 Figure 48. Quad-Speed (slow) Stopband Rejection................................................................................... 48 Figure 49. Quad-Speed (slow) Transition Band......................................................................................... 48 Figure 50. Quad-Speed (slow) Transition Band (detail)............................................................................. 48 Figure 51. Quad-Speed (slow) Passband Ripple....................................................................................... 48 4 CS4384 DS620F1 ...
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... Table 4. PCM Digital Interface Format, Hardware Mode Options............................................................. 21 Table 5. Mode Selection, Hardware Mode Options .................................................................................. 21 Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 21 Table 7. Digital Interface Formats - PCM Mode........................................................................................ 37 Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 37 Table 9. ATAPI Decode ............................................................................................................................ 43 Table 10. Example Digital Volume Settings .............................................................................................. 44 DS620F1 CS4384 5 ...
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... DSD3 1 DSD2 2 DSD1 GND 5 MCLK 6 CS4384 LRCK 7 8 SDIN1 SCLK 9 10 SDIN2 Pin Description CS4384 36 TST_OUT 35 AOUT3 34 AOUT4 33 TST_OUT GND 30 TST_OUT 29 AOUT5 28 AOUT6 27 TST_OUT 26 TST_OUT 25 AOUT7 Table 1 illus- DS620F1 ...
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... Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSD5, DSD6 47,46 DSD7, DSD8 45, 44 DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface. DS620F1 Pin Description ® mode as shown in the Typical Connection Dia- CS4384 Tables 4 ™ mode. 7 ...
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... Digital internal power VD VLS Control port interface power VLC Any Pin Except Supplies I in Serial data port interface V IND-S Control port interface V IND stg CS4384 Min Typ Max 4.75 5.0 5.25 2.37 2.5 2.63 1.71 5.0 5.25 1.71 5.0 5.25 -40 - +85 ...
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... A-weighted (Note 2) unweighted 24-bit -0 dB THD+N -20 dB -60 dB 16-bit 0 dB - kHz) PCM, DSD processor V 64%•V FS Direct DSD Mode 47%•V Z OUT I OUTmax QMAX and includes attenuation due CS4384 C; Full-Scale 997 Hz ° Min Typ Max 97 103 - 94 100 - - -88 -82 - -80 -74 - -40 - ...
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... Valid with the recommended capacitor values on FILT+ and VQ as shown in 10 Symbol normal operation, VA VD= 2 Interface current, VLC VLS power-down state (all supplies 2.5 V normal operation (Note 6) power-down θ multi-layer JA θ dual-layer JA θ kHz) PSRR (60 Hz) CS4384 Min Typ Max Units - µ µ µA - 200 - - 465 520 ...
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... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .583 (Note 10 6.15/Fs to -0.01 dB corner corner kHz -0.01 .635 (Note 10 7.1/Fs “Filter Response Plots” on page CS4384 Typ Max Unit - .454 Fs - .499 Fs - +0. ±0. ±0. ±0. .430 Fs - .499 ...
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... Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .792 (Note 10 5.4/Fs to -0.01 dB corner corner kHz -0.01 .868 (Note 10 6.6/Fs Min corner kHz -0. -0.1 dB corner corner 0 -0.1 CS4384 (Note 8) Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. ±0. ±0. ±0. .296 Fs - .499 Fs - +0.01 ...
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... MUTEC Low-Level Output Voltage 13. Any pin except supplies. Transient currents ±100 mA on the input pins will not cause SCR latch-up DS620F1 Symbol (Note 13 Serial I Control I Serial I Control I Control I Control I/O = 1 max CS4384 Min Typ Max Units µ ± ...
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... L Symbol (Note 14) (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode (Note 16) LRCK t t sckl lcks SCLK MSB-1 SDIN1 Figure 2. TDM Serial Audio Interface Timing CS4384 Min Max Units 1.024 55.2 MHz kHz 108 kHz ...
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... Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode DS620F1 = 30 pF) L Symbol Min 40 t 160 sclkl t 160 sclkh (64x Oversampled) 1.024 (128x Oversampled) 2.048 t 20 sdlrs t 20 sdh t -20 dpm t sclkh t sclkl t t sdlrs sdh t t dpm dpm CS4384 Typ Max Unit - 3.2 MHz - 6.4 MHz - - ...
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... high t t sud t sust hdd Figure 5. Control Port Timing - I²C Format CS4384 Min Max Unit - 100 kHz 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop ...
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... L Symbol f sclk t srs (Note 18) t spi t csh t css t scl t sch t dsu (Note 19 (Note 20 (Note 20 css t scl t sch dsu t dh Figure 6. Control Port Timing - SPI Format CS4384 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... RST 15 SCL/CCLK 16 FILT+ SDA/CDIN 17 ADO/CS Note* 18 VLC TST_OUT 0.1 µF GND GND TST *Pins 10, 12 CS4384 + 0.1 µF 1 µF Analog Conditioning 39 and Muting Analog Conditioning 38 and Muting Analog Conditioning 35 and Muting Analog Conditioning 34 and Muting Analog Conditioning 29 and Muting Analog Conditioning 28 ...
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... K Ω FILT RST 18 VLC 0.1 µF TST_OUT GND GND 5 31 CS4384 + 0.1 µF 1 µF Analog Conditioning 39 and Muting Analog Conditioning 38 and Muting Analog Conditioning 35 and Muting Analog Conditioning 34 and Muting Analog Conditioning 29 and Muting Analog Conditioning 28 and Muting Analog Conditioning ...
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... SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces see AN282 “The 2-Channel Serial Audio Interface: A Tutorial”. The CS4384 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode through I²C or SPI. ...
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... DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate CS4384 FORMAT FIGURE 0 ...
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... Figure 12. Format 3 - Right-Justified 24-bit Data 32 clocks LRCK Left Channel SCLK SDINx Figure 13. Format 4 - Right-Justified 20-bit Data 32 clocks LSB MSB + LSB MSB Figure 10. Format 1 - I² 24-bit Data CS4384 Figures Right Channel + LSB Right Channel + LSB Right Channel Right Channel Right Channel DS620F1 9-19. ...
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... DAC_B4 20 clks Figure 15. Format 8 - One Line Mode 1 LSB MSB LSB MSB DAC_A3 DAC_B1 24 clks 24 clks DAC_B4 24 clks Figure 16. Format 9 - One Line Mode 2 CS4384 Right Channel clks Right Channel LSB MSB LSB MSB LSB DAC_B2 DAC_B3 20 clks 20 clks 128 clks ...
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... Figure 18. Format 11 - One Line Mode 4 256 clks LSB MSB LSB MSB LSB MSB DAC_A2 DAC_B2 DAC_A3 32 clks 32 clks 32 clks Figure 19. Format 12 - TDM Mode CS4384 128 clks Right Channel MSB LSB MSB LSB MSB LSB DAC_B2 DAC_B3 DAC_B4 20 clks 20 clks 20 clks 128 clks ...
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... The auto speed-mode detect feature allows for the automatic selection of speed mode based off of the in- coming sample rate. This allows the CS4384 to accept a wide range of sample rates with no external inter- vention necessary. The auto speed-mode detect feature is available in both Hardware and Software Mode. ...
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... CS4384, but may lower the sensitivity to board level routing of the DSD data signals. The CS4384 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4384 to alter the incoming invalid DSD data. ...
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... The Typical Connection Diagram shows the rec- ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4384 should be connect the analog ground plane. ...
Page 28
... The external mute circuitry needs to be self biased into an active state in order to be muted during reset. Upon release of reset, the CS4384 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The ex- ternal-bias voltage level that the MUTEC pins see at the time of release of reset must meet the “ ...
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... Hardware sequence has begun advised that if the CPEN bit can not be set in time then the SDINx pins should remain static low (this way no audio data can be DS620F1 Figure 25. Recommended Mute Circuitry Section 4.1. In this state, the registers are reset to the default CS4384 Section 4.1. In this state, the 29 ...
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... There pin. Pin AD0 en- bus followed by the address byte. The upper 6 bits must be I²C 4.14.1) is set to 1, repeat the previous step until all the desired registers writes to other registers are desired necessary to initiate I²C CS4384 writes or reads and I²C DS620F1 ...
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... I²C Read section further reads from other registers are de- I² 1-8 Figure 26. Control Port Timing, I²C Mode 4.14.1) is set to 1, repeat the previous step until all the desired registers CS4384 read is the first operation performed on the I² 1-8 S top Write 31 ...
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... INCR (Auto Map Increment Enable) Default = ‘0’ Disabled 1 - Enabled 4.15.2 MAP4-0 (Memory Address Pointer) Default = ‘00000’ 0011000 yte ory A d dress P oin te r Figure 27. Control Port Timing, SPI Mode MAP4 MAP3 CS4384 LSB byte MAP2 MAP1 MAP0 DS620F1 ...
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... P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 A2_VOL6 A2_VOL5 A2_VOL4 B2_VOL6 B2_VOL5 B2_VOL4 P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 A3_VOL6 A3_VOL5 A3_VOL4 B3_VOL6 B3_VOL5 B3_VOL4 P4_DEM1 P4_DEM0 P4ATAPI4 P4ATAPI3 CS4384 PART0 REV2 REV1 Reserved Reserved FM1 INVALID_D DSD_PM_ DSD_PM_ Reserved Reserved Reserved INV_B2 INV_A2 INV_B1 0 ...
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... Addr Function 7 14h Vol. Control A4 A4_VOL7 default 0 15h Vol. Control B4 B4_VOL7 default 0 16h PCM clock mode Reserved default A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 Reserved MCLKDIV Reserved Reserved CS4384 A4_VOL2 A4_VOL1 A4_VOL0 B4_VOL2 B4_VOL1 B4_VOL0 Reserved Reserved Reserved DS620F1 ...
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... PART4 PART3 PART2 0 0 6.1.1 Part Number ID (PART) [Read Only] 00000- CS4384 6.1.2 Revision ID (REV) [Read Only] 000 - Revision A0 001 - Revision B0 Function: This read-only register can be used to identify the model and revision number of the device. 6.2 Mode Control 1 (Address 02h) ...
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... Interface Format and the options are detailed in Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set to ensure proper switching from one mode to another DIF0 Reserved Figures 9-19. CS4384 Digital Interface Reserved FM1 FM0 DS620F1 ...
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... DSD data with a 2x MCLK to DSD data rate. 1 128x oversampled DSD data with a 3x MCLK to DSD data rate. 0 128x oversampled DSD data with a 4x MCLK to DSD data rate. 1 128x oversampled DSD data with a 6x MCLK to DSD data rate. Table 8. Digital Interface Formats - DSD Mode CS4384 Format FIGURE ...
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... DSD Phase Modulation Mode Enable (DSD_PM_EN) Function: When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode). 38 25.) CS4384 Section 2), the dynamic range DS620F1 ...
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... MUTEC1 and MUTEC234 pins in 6.7.2 Channel A Volume = Channel B Volume (Px_A=B) Default = Disabled 1 - Enabled Function: DS620F1 Reserved Reserved INV_A3 INV_B2 P1_A=B P2_A CS4384 Reserved Reserved FILT_SEL INV_A2 INV_B1 INV_A1 P3_A=B P4_A=B SNGLVOL Section 4.11. 39 ...
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... The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10 21 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel RMP_DN PAMUTE CS4384 DAMUTE MUTE_P1 MUTE_P0 DS620F1 ...
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... The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. 6.8.6 MUTE Polarity and DETECT (MUTEP1:0) Default = Auto polarity detect, selected from MUTEC1 pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity DS620F1 CS4384 41 ...
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... Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re- sponse at 32, 44 kHz sample rates. De-emphasis is only available in Single-Speed Mode. 42 for the description MUTE_A3 MUTE_B2 PxATAPI4 PxATAPI3 (Figure 20 on page CS4384 MUTE_A2 MUTE_B1 MUTE_A1 PxATAPI2 PxATAPI1 PxATAPI0 25) DS620F1 ...
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... ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 DS620F1 Table 9 and Figure 21 ATAPI1 ...
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... Table 10 are approximate. The actual attenuation is determined Decimal Value 00000000 0 00000001 1 00000110 6 11111111 255 Table 10. Example Digital Volume Settings Reserved Reserved CS4384 xx_VOL2 xx_VOL1 xx_VOL0 Table 10. The volume changes are imple- Volume Setting 0 dB -0.5 dB -3.0 dB -127 Reserved Reserved Reserved ...
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... Figure 31. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 33. Single-Speed (slow) Transition Band CS4384 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0 ...
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... Figure 37. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 39. Double-Speed (fast) Passband Ripple CS4384 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...
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... Figure 43. Double-Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 45. Quad-Speed (fast) Transition Band CS4384 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...
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... Figure 49. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0 0.02 0.52 0.53 0.54 0.55 Figure 51. Quad-Speed (slow) Passband Ripple CS4384 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...
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... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS620F1 CS4384 49 ...
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... Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 CS4384 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9 ...
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... Changes “DAC Pair Disable (DACx_DIS)” on page 36 “Mode Select” on page 21 “DAC Analog Characteristics” on page 9 “IMPORTANT NOTICE” on page 51 CS4384 Container Order # Tray CS4384-CQZ Tape & Reel CS4384-CQZR - - CDB4384 “Digital Interface Format (DIF)” on page 36 Power and Thermal Characteristics 51 ...
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... CS4384 DS620F1 ...