CS4391A-KZZ Cirrus Logic Inc, CS4391A-KZZ Datasheet
CS4391A-KZZ
Specifications of CS4391A-KZZ
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CS4391A-KZZ Summary of contents
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... DSD audio data, consumes very little power and operates over a wide power supply range. These features are ideal for DVD, A/V receivers, CD and set-top box systems. ORDERING INFORMATION CS4391A-KS CS4391A-KZ CS4391A-KZZ 20-pin TSSOP, Lead Free - °C CDB4391A (SCL/CCLK) (AD0/CS) ...
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... I C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. 2 CS4391A 2 C Patent Rights to use DS600PP3 ...
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... Table 12. Single Speed Only ( kHz) De-Emphasis, Stand-Alone Mode Options ..................... 29 Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options......... 29 Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ......... 30 Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options ................................................... 30 Table 16. Memory Address Pointer (MAP) .......................................................................................... 35 DS600PP3 ................................................................................................. 39 CS4391A 3 ...
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... Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 32 Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 32 Figure 13. De-Emphasis Curve ..................................................................................................... 32 Figure 14. ATAPI Block Diagram .................................................................................................. 32 Figure 15. CS4391A Output Filter ................................................................................................. 33 Figure 16. Control Port Timing, SPI mode .................................................................................... 35 Figure 17. Control Port Timing, I Figure 18. Single-Speed Frequency Response ............................................................................ 36 Figure 19 ...
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... Symbol Min VA 4.75 VL 1.8 -KS & -KZ T -10 A (AGND = 0 V; all voltages with respect to ground.) Symbol Min VA -0 -0.3 IND T - -65 stg CS4391A Typ Max Units 5.0 5. °C Max Units 6 ±10 mA VL+0.4 V 125 °C 150 °C 5 ...
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... Input test signal is a Symbol (Note 1) unweighted A-Weighted A-Weighted (Note 1,2) THD - kHz) normal operation power-down state normal operation power-down (Note 3) PSRR (60 Hz) Symbol Min 1.05VA CMOUT - - - CS4391A = 5 kΩ pF Min Typ Max Unit 100 105 - dB 103 108 - dB - 102 - dB - - -45 - 108 - dB - 100 ...
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... kHz Fs = 44.1 kHz kHz Fs = 44.1 kHz (Note 4) to -0.1 dB corner corner 0 -0.1 .577 (Note 5) 55 tgd kHz (Note corner 0 -0.7 (Note corner 0 -0.7 CS4391A Typ Max Unit - .4535 Fs - .4998 Fs - +.035 9/ ±0.36/ +.2/-. ...
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... DIGITAL CHARACTERISTICS Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current 8 (AGND = 0 V; all voltages with respect to ground.) Symbol Min V 70 CS4391A Typ Max Units - - VL - 20% VL µA - ± DS600PP3 ...
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... Notes: 6. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled DS600PP3 Symbol Fs (Note 6) t slrd t slrs t sdlrs t sdh t slrs t s lrd lrs Figure 1. Serial Mode Input Timing CS4391A (Inputs: Logic Logic 1 = VL) Min Typ Max 4 - 200 MCLK MCLK ...
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... SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Figure 2. Direct Stream Digital - Serial Audio Input Timing 10 (Logic 0 = AGND = DGND; Logic 1 = VL) Symbol Min Typ sclkl t 20 sclkh 20 t sclkw t 20 sdlrs t 20 sdh t sclkh t sclkl dlrs sd h CS4391A Max Unit DS600PP3 ...
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... DS600PP3 2 C CONTROL PORT Symbol hdst t low t high t sust (Note 7) t hdd t sud t susp ted t high t hdst sud lo w hdd 2 Figure Control Port Timing CS4391A (Inputs: logic 0 = AGND, Min Max - 100 scl 500 - irs 4.7 - buf 4.0 - 4.7 - 4 250 - 300 f 4 ...
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... Symbol f sclk t srs (Note 8) t spi t csh t css t scl t sch t dsu (Note (Note 10 (Note 10 srs t spi t css t scl t sch Figure 4. SPI Control Port Timing CS4391A (Inputs: logic 0 = AGND, Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... Figure 5. Typical Connection Diagram - PCM Mode * A high logic level for all digital inputs should not exceed VL. DS600PP3 0.1 µ 0 FILT (SCL/CCLK 391A AMUTEC RST CMOUT CS4391A +5V Analog µ 0.1 µf + 1.0 µ log C onditioning & ute log C onditioning & ute 12 1.0 µ ...
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... Figure 6. Typical Connection Diagram - DSD Mode * A high logic level for all digital inputs should not exceed VL FILT + DIN ) ( CS4391A DSD_MODE CMOUT CS4391A +5V Analog µ + 1.0 f 0.1 µ 0.1 µf 1.0 µ itionin g & ute log ition in g & 1.0 µ DS600PP3 ...
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... FM1, FM0 (Functional Mode). See Table 4 Default = ‘00’ Single-Speed Mode ( kHz sample rates Double-Speed Mode (50 to 100 kHz sample rates Quad-Speed Mode (100 to 200 kHz sample rates Direct Stream Digital Mode DS600PP3 DIF1 DIF0 DEM1 24-bit data CS4391A DEM0 FM1 FM0 ...
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... CHANNEL A VOLUME CONTROL (ADDRESS 03H) See Channel B Volume Control (address 04h) 3.4 CHANNEL B VOLUME CONTROL (ADDRESS 04H MUTE VOL6 VOL5 0 0 MUTE Default = ‘0’ Disabled 1 - Enabled Volume Default = ‘0’ (Refer to Table ATAPI4 ATAPI3 VOL4 VOL3 CS4391A ATAPI2 ATAPI1 ATAPI0 VOL2 VOL1 VOL0 DS600PP3 ...
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... Default = ‘0’ Disabled (Stand-Alone Mode Enabled (Control Port Mode) PDN (Power-Down) Default =’1’ Disabled 1 - Enabled MUTEC A=B Default = ‘0’ Disabled 1 - Enabled FREEZE Default = Disabled 1 - Enabled MCLK Divide Default = Disabled 1 - Enabled DS600PP3 PDN MUTEC CS4391A FREEZE MCLK Divide Reserved ...
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... NOTE: De-emphasis is available only in Single-Speed Mode. See Table 3 4.1.4 Functional Mode (Bits 1:0) Function: Selects the required range of input sample rates or DSD Mode. See Table DIF1 DIF0 DEM1 CS4391A DEM0 FM1 FM0 DS600PP3 ...
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... See Table 5 4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) Function: The CS4391A implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 6 4.3 CHANNEL A VOLUME CONTROL - ADDRESS 03H See Section 4.4 Channel B Volume Control - Address 04h ...
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... AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid VOL4 VOL3 PDN MUTEC CS4391A VOL2 VOL1 VOL0 FREEZE MCLK Divide Reserved DS600PP3 ...
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... Freeze Bit, make all register changes, then Disable the Freeze bit. 4.5.6 Master Clock Divide (Bit 1) Function: This function allows the user to select an internal divide the Master Clock. This selection is required to access the higher Master Clock rates as shown in Table 9. DS600PP3 CS4391A 21 ...
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... VL AOUTA SDATA AOUTA SCLK LRCK AGND 6 MCLK 15 AOUTB AOUTB BMUTEC 9 12 CMOUT 10 11 FILT+ CS4391A Channel A Mute Control Differential Output Differential Output Analog Power Analog Ground Differential Output Differential Output Channel B Mute Control Common Mode Voltage Positive Voltage Reference DS600PP3 ...
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... Pins and 10 Inputs Function: The Mode Select Pins, M0-M3, select the operational mode of the device as detailed in Tables 11-15. Mode Select - M3 (Control Port Mode) Pin 7, Input Function: The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground. DS600PP3 CS4391A 23 ...
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... These pins are intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. 24 CS4391A DS600PP3 ...
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... Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA- Pins 14, 15 and 18, 19, Outputs Function: The full scale differential analog output level is specified in the Analog Characteristics specifications table. Analog Ground - AGND Pin 16, Input Function: Analog ground reference. Analog Power - VA Pin 17, Input Function: Analog power supply. DS600PP3 CS4391A 25 ...
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... AGND 6 MCLK 15 AOUTB AOUTB BMUTEC 9 12 CMOUT 10 11 FILT+ CS4391A Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode DS600PP3 ...
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... DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 2. Digital Interface Formats - DSD Mode DESCRIPTION MODE Mode CS4391A DESCRIPTION DESCRIPTION 27 ...
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... Table 6. ATAPI Decode Volume Setting -20 dB -40 dB -60 dB -90 dB CS4391A AOUTA AOUTB MUTE MUTE MUTE bR MUTE bL MUTE b[(L+R)/2] aR MUTE b[(L+R)/2] aL MUTE b[(L+R)/2] a[(L+R)/2] MUTE a[(L+R)/2] bR a[(L+R)/2] bL a[(L+R)/2] b[(L+R)/2] MUTE MUTE MUTE bR MUTE bL MUTE [(bL+aR)/2] aR ...
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... Right Justified, 16-bit Data Right Justified, 24-bit Data DESCRIPTION M0 DESCRIPTION Left Justified up to 24-bit data 24-bit data Right Justified 16-bit data 0 Right Justified 24-bit data 1 CS4391A See Note 768x 1024x 24.5760 32.7680 33.8688 45.1584 36.8640 49.1520 See Note 384x 512x 24.5760 32.7680 33 ...
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... DSD data with a 2x MCLK to DSD data rate 0 128x oversampled DSD data with a 3x MCLK to DSD data rate 1 128x oversampled DSD data with a 4x MCLK to DSD data rate 0 128x oversampled DSD data with a 6x MCLK to DSD data rate 1 CS4391A FORMAT DESCRIPTION FIGURE ...
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... Figure 7. Format 0, Left Justified up to 24-Bit Data L eft LRCK SCLK SDATA clo cks Figure 9. Format 2, Right Justified 16-Bit Data LRCK SCLK SDATA clo cks DS600PP3 + MSB - Figure 8. Format 24-Bit Data Figure 10. Format 3, Right Justified 24-Bit Data CS4391A R igh LSB R igh LSB ...
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... Left Channel Audio Data Right Channel Audio Data Gain dB T1=50 µs 0dB -10dB F1 F2 3.183 kHz 10.61 kHz Figure 13. De-Emphasis Curve A Channel Volume Control Σ B Channel Volume Control Figure 14. ATAPI Block Diagram CS4391A µs Frequency MUTE AoutA Σ MUTE AoutB DS600PP3 ...
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... Butterworth filter and differential to single- ended converter which was implemented on the CS4391A evaluation board, CDB4391A. The CS4391A filter, as seen in Figure 14 linear phase design and does not include phase or ampli- tude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry ...
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... The control port has 2 modes: SPI and I CS4391A operating as a slave device in both 2 modes operation is desired, AD0/CS should be tied AGND. If the CS4391A ever de- tects a high to low transition on AD0/CS after pow- er-up, SPI mode will be selected. The control port registers are write-only in SPI mode. 8.1 ...
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... N ote pera tion rite byte co ntain s the M em ory inter DS600PP3 Reserved Reserved Table 16. Memory Address Pointer (MAP ADDRESS R/W MSB b yte ory Figure 16. Control Port Timing, SPI mode N ote Figure 17. Control Port Timing, I CS4391A 2 1 MAP2 MAP1 0 0 DATA yte 1-8 Stop 2 C Mode 0 MAP0 0 35 ...
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... Frequency (normalized to Fs) Figure 22. Double-Speed Frequency Response 36 0.3 0.35 0.4 0.45 0.5 Figure 19. Single-Speed Transition Band Figure 21. Single-Speed Stopband Rejection 0.3 0.35 0.4 0.45 0.5 Figure 23. Double-Speed Transition Band CS4391A DS600PP3 ...
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... Figure 24. Double-Speed Transition Band DS600PP3 Figure 25. Double-Speed Stopband Rejection CS4391A 37 ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4391A Evaluation Board Datasheet 2 3. “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com 38 CS4391A DS600PP3 ...
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... JEDEC #: MO-153 Controlling Dimension is Millimeters. CS4391A 1 E1 END VIEW L MILLIMETERS NOM MAX -- -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 6.50 6.60 6.40 6.50 4.40 4 ...
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... JEDEC #: MS-013 Controlling Dimension is Millimeters CS4391A MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.43 0.51 0.23 0.28 ...