AD9762ARUZ Analog Devices Inc, AD9762ARUZ Datasheet - Page 13

• Manufacturer Part Number: AD9762ARUZ
• Description: IC DAC 12BIT 125MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9762ARUZ

• Data Interface: Parallel
• Settling Time: 35ns
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 160mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9762-EB - BOARD EVAL FOR AD9762
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I
varied by an external voltage, V
fier. An example of this method is shown in Figure 44 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
referenced to ACOM and should not exceed 1.2 V. The value
of R
and 625 µA, respectively. The associated equations in Figure 44
can be used to determine the value of R
In some applications, the user may elect to use an external con-
trol amplifier to enhance the multiplying bandwidth, distortion
performance, and/or settling time. External amplifiers capable
of driving a 50 pF load such as the AD817 are suitable for this
purpose. It is configured in such a way that it is in parallel with
the weaker internal reference amplifier as shown in Figure 45.
In this case, the external amplifier simply overdrives the weaker
reference control amplifier. Also, since the internal control
amplifier has a limited current output, it will sustain no damage
if overdriven.
REV. B
Amplifier
Figure 45. Configuring an External Reference Control
SET
V
1 F
is such that I
Figure 44. Dual-Supply Gain Control Circuit
GC
INPUT
V
REF
R
SET
CONTROL AMPLIFIER
R
SET
EXTERNAL
REFMAX
I
I
WITH V
REF
REF
AD1580
= (1.2–V
REFIO
FS ADJ
AD9762
+1.2V REF
GC
REFIO
FS ADJ
1.2V
+1.2V REF
AD9762
and I
< V
AVDD
GC
REFLO
GC
REFIO
REFLO
)/R
BANDLIMITING
, applied to R
REFMIN
SET
CAPACITOR
AND 62.5 A
OPTIONAL
50pF
OUT1
OUT2
SET
50pF
do not exceed 62.5 µA
Figure 43. Single-Supply Gain Control Circuit
COMP1
.
AGND
COMP1
R
CURRENT
SOURCE
FB
ARRAY
AD7524
AVDD
CURRENT
I
SET
SOURCE
REF
ARRAY
AVDD
AVDD
DB7–DB0
AVDD
via an ampli-
625A
V
DD
V
REF
REF
GC
R
, is
SET
is
0.1V TO 1.2V
–13–
I
V
REF
REF
ANALOG OUTPUTS
The AD9762 produces two complementary current outputs,
I
differential operation. I
complementary single-ended voltage outputs, V
via a load resistor, R
Function section by Equations 5 through 8. The differential
voltage, V
converted to a single-ended voltage via a transformer or differ-
ential amplifier configuration. The ac performance of the
AD9762 is optimum and specified using a differential trans-
former coupled output in which the voltage swing at I
I
desirable, I
The distortion and noise performance of the AD9762 can be
enhanced when the AD9762 is configured for differential opera-
tion. The common-mode error sources of both I
can be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed wave-
form increases. This is due to the first order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the recon-
structed signal power to the load (i.e., assuming no source
termination). Since the output currents of I
complementary, they become additive when processed differen-
tially. A properly selected transformer will allow the AD9762 to
provide the required power and voltage levels to different loads.
Refer to Applying the AD9762 section for examples of various
output configurations.
The output impedance of I
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V
As a result, maintaining I
via an I-V op amp configuration will result in the optimum dc
linearity. Note, the INL/DNL specifications for the AD9762
are measured with I
op amp.
=
OUTA
OUTB
/R
SET
is limited to ± 0.5 V. If a single-ended unipolar output is
and I
REFIO
FS ADJ
OUTA
+1.2V REF
AD9762
DIFF
OUTA
OUTB
and V
REFLO
, existing between V
BANDLIMITING
CAPACITOR
, which may be configured for single-ended or
should be selected.
OPTIONAL
OUTB
OUTA
LOAD
50pF
) due to the nature of a PMOS device.
OUTA
, as described in the DAC Transfer
OUTA
maintained at a virtual ground via an
COMP1
OUTA
and I
CURRENT
SOURCE
and/or I
ARRAY
AVDD
and I
OUTB
AVDD
OUTA
OUTB
OUTB
can be converted into
and V
is determined by the
OUTA
at a virtual ground
OUTB
OUTA
AD9762
OUTA
and I
can also be
and V
OUTA
and I
OUTB
OUTB
and
OUTB
are
,