CS4398-CZZ Cirrus Logic Inc, CS4398-CZZ Datasheet
CS4398-CZZ
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CS4398-CZZ Summary of contents
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... Volume Control Interpolation Multibit Filter with Modulator ∆Σ Volume Control DSD Processor -Volume control -50kHz filter Direct DSD Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) CS4398 5 V Switched Left Capacitor Differential DAC and Output Filter Switched Right Capacitor Differential ...
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... DSD audio data, has selectable dig- ital filters, consumes little power, and delivers excellent sound quality. Package Pb-Free Grade 28-pin YES Commercial TSSOP - - CS4398 Temp Range Container Order # Rail CS4398-CZZ -10° to +70° C Tape & Reel CS4398-CZZR - - CDB4398 DS568F1 ...
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... Channel B Volume Control - Register 06h ....................................................................... 34 7.7 Ramp and Filter Control - Register 07h ........................................................................... 35 7.8 Misc. Control - Register 08h ............................................................................................ 37 7.9 Misc. Control - Register 09h ............................................................................................ 38 8. PARAMETER DEFINITIONS .................................................................................................. 39 9. REFERENCES ........................................................................................................................ 39 10. PACKAGE DIMENSIONS .................................................................................................... 40 10.1 28-TSSOP ..................................................................................................................... 40 THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................... 40 11. APPENDIX ....................................................................................................................... 41 DS568F1 .................................................................................. 19 CS4398 3 ...
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... Figure 36. Quad-Speed (fast) Stopband Rejection ....................................................................... 43 Figure 37. Quad-Speed (fast) Transition Band ............................................................................. 43 Figure 38. Quad-Speed (fast) Transition Band (detail) ................................................................. 44 Figure 39. Quad-Speed (fast) Passband Ripple ........................................................................... 44 Figure 40. Quad-Speed (slow) Stopband Rejection...................................................................... 44 Figure 41. Quad-Speed (slow) Transition Band............................................................................ 44 Figure 42. Quad-Speed (slow) Transition Band (detail)................................................................ 44 Figure 43. Quad-Speed (slow) Passband Ripple.......................................................................... 44 4 CS4398 DS568F1 ...
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... Table 1. Clock Ratios .................................................................................................................... 21 Table 2. Common Clock Frequencies........................................................................................... 22 Table 3. Digital Interface Format, Stand-Alone Mode Options...................................................... 22 Table 4. Mode Selection, Stand-Alone Mode Options .................................................................. 22 Table 5. Digital Interface Formats - PCM Mode............................................................................ 29 Table 6. Digital Interface Formats - DSD Mode ............................................................................ 30 Table 7. Example Digital Volume Settings .................................................................................... 34 Table 8. Revision Table ................................................................................................................ 45 DS568F1 CS4398 5 ...
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... PINOUT DRAWING DSD_B DSD_SCLK SDIN SCLK LRCK MCLK VD DGND M3 (AD1/CDIN) M2 (SCL/CCLK) M1 (SDA/CDOUT) M0 (AD0/CS) RST VLC Figure 1. Pinout Drawing CS4398 DSD_A VLS VQ AMUTEC AOUTA- AOUTA+ VA AGND AOUTB+ AOUTB- BMUTEC VREF REF_GND FILT+ DS568F1 ...
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... I²C mode. CDOUT is the output data line for the Control Port interface in SPI mode. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin AD0/ I²C mode the chip select signal for SPI format. DS568F1 Pin Description CS4398 7 ...
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... Voltage reference VREF Digital power VD VLS VLC any pin except supplies I in Serial audio interface V IN-LS Control port interface V IN- stg CS4398 = 25 ° 5 3.3 V.) A Min Typ Max 4.75 5.0 5.25 4.75 5.0 5.25 3.1 3.3 5.25 1.7 3.3 5.25 1.7 3 ...
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... A-Weighted (Note 2) unweighted (Note 1) THD+N 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB (Note 2) -20 dB -60 dB A-Weighted unweighted (Note 3) THD - kHz) ICGM PCM, DSD processor Direct DSD mode Z OUT CS4398 Min Typ Max 114 120 - 111 117 - - -107 -100 - - - - - ...
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... Amplitude vs. Frequency plots of this data are available in the “Appendix” on page 41. 10 Fast Roll-Off Min to -0.01 dB corner corner 0 -0.01 0.547 (Note 7) 102 - kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner 0 -0.01 .583 (Note -0.01 dB corner corner 0 -0.01 .635 (Note CS4398 Typ Max Unit - .454 Fs - .499 Fs - +0. 9.4/ ±0. ±0. ±0. .430 Fs - .499 ...
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... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner 0 -0.01 .792 (Note -0.01 dB corner corner 0 -0.01 .868 (Note Min corner 0 -0. -0.1 dB corner corner 0 -0.1 CS4398 Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. 6.65/ ±0. ±0. ±0. .296 Fs - .499 ...
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... Quad-Speed Mode Fs See Tables 1 & 2 (page 21) for compatible frequencies t sclkl t sclkh Single-Speed Mode t sclkw t sclkw Quad-Speed Mode t sclkw t slrd t slrs t sdlrs t sdh t slrs t slrd t sdlrs Figure 2. Serial Mode Input Timing CS4398 Min Typ Max 108 100 - 216 40% - 60% 45 -------------------- - - - ( ...
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... Figure 5. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. Format 4, Right-Justified 20-Bit Data. (Available in Control Port Mode only) Format 5, Right-Justified 18-Bit Data. (Available in Control Port Mode only) DS568F1 + LSB LSB MSB - Figure 4. Format 1 - I² 24-bit Data + CS4398 nel + LSB nel + LSB ...
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... Figure 7. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode pF) L Symbol t sclkl t sclkh (64x Oversampled) (128x Oversampled) t sdlrs t sdh t dpm t sclkh t sclkl t t sdlrs sdh CS4398 Min Typ Max Unit 160 - - ns 160 - - ns 1.024 - 3.2 MHz 2.048 - 6.4 MHz ...
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... Symbol f scl t irs t buf t hdst t low t high t sust (Note 10) t hdd t sud susp t ack t high t t sud t ack hdd Figure 8. Control Port Timing - I²C Format CS4398 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL top ...
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... L Symbol f sclk t srs (Note 11) t spi t csh t css t scl t sch t dsu (Note 12 (Note 13 (Note 13 (Note 14) t scdov (Note 15) t cscdo t css t scl t sch dsu scdov scdo v CS4398 FORMAT ™ Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... Valid with the recommended capacitor values on FILT+ and V gram” on page 19. 21. This current is sourced/sinked directly from the VA supply. DS568F1 Symbol (Note 17 ref ref 3 Interface current (Note kHz) PSRR (60 Hz Qmax (Note 21 CS4398 Min Typ Max - 1 258 340 - 192 240 - 200 - - 0.5• ...
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... Low-Level Output Voltage (I = 1.2 mA) OL MUTEC auto detect input high voltage MUTEC auto detect input low voltage 18 Symbol Min Serial I/O V 70% IH Control I/O V 70% IH Serial I Control I Control I/O V 80% OH Control I 70% CS4398 Typ Max Units µA - ± 30% VA DS568F1 ...
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... SCLK LRCK SDIN VLS DSD_SCLK DSD_A DSD_B BMUTEC CS4398 VLC M0 (AD0/CS) M1 (SDA/CDOUT) M2 (SCL/CCLK) REF_GND M3 (AD1/CDIN) RST DGND AGND Figure 10. Typical Connection Diagram CS4398 +5V 0 Left Channel Analog AOUTA - Conditioning and Mute AOUTA+ AOUTB+ Right Channel Analog AOUTB - Conditioning and Mute VQ FILT+ ...
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... The external mute circuitry needs to be self-biased into an active state in order to be muted during reset. Upon release of reset, the CS4398 detects the status of the MUTEC pins (high or low) and then selects that state as the polarity to drive when the mutes become active. The external- bias voltage level that the MUTEC pins see at the time of release of reset must meet the “ ...
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... Oversampling Modes The CS4398 operates in one of three oversampling modes based on the input sample rate. Single-Speed mode supports input sample rates kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode sup- ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x ...
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... Table 2. Common Clock Frequencies Description Left-Justified 24-bit data I² 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Description CS4398 MCLKDIV2 MCLKDIV3 768x 1024x 1152x 24.5760 32.7680 36.8640 33.8688 45.1584 - 36.8640 49.1520 - 384x ...
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... Interpolation Filter (Control Port Mode) To accommodate the increasingly complex requirements of digital audio systems, the CS4398 incorpo- rates selectable interpolation filters. A fast and a slow roll-off filter are available in each of Single-, Double- , and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles ...
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... CS4398, but may lower the sensitivity to board-level routing of the DSD data signals. The CS4398 can detect errors in the DSD data that do not comply to the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 09h) allow the CS4398 to alter the incoming invalid DSD da- ta ...
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... Format Selection The Control Port has two formats: SPI and I²C, with the CS4398 operating as a slave device. If I²C operation is desired, AD0/CS should be tied to VLC or GND. If the CS4398 ever detects a high-to-low transition on AD0/CS after power-up, SPI format will automatically be selected. ...
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... SPI Format In SPI format the CS4398 chip select signal; CCLK is the Control Port bit clock; CDIN is the input data line from the microcontroller; CDOUT is the output data line and the chip address is 1001100. CS, CCLK,and CDIN are all inputs, and data is clocked in on the rising edge of CCLK. CDOUT is an output and is high-impedance when not actively outputting data ...
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... MAP. To read multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high. The CDOUT line will high-impedance state once CS goes high Figure 16. Control Port Timing, SPI Format (Read) DS568F1 MAP MSB R/W MAP = Memory Address Pointer yte 1 CS4398 DATA LSB byte 1 byte ...
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... DAMUTE MUTEC MUTE_A A VOL6 VOL5 VOL4 VOL6 VOL5 VOL4 SZC0 RMP_UP RMP_DN CPEN FREEZE MCLKDIV2 MCLKDIV3 Reserved Reserved Reserved Reserved Reserved CS4398 PART0 REV2 REV1 DEM1 DEM0 FM1 ATAPI3 ATAPI2 ATAPI1 ATAPI0 MUTE_B Reserved MUTEP1 MUTEP0 VOL3 VOL2 VOL1 VOL3 VOL2 ...
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... DIF0 DEM1 Description 0 Left-Justified 24-bit data 1 I² 24-bit data 0 Right-Justified, 16-bit data 1 Right-Justified, 24-bit data 0 Right-Justified, 20-bit data 1 Right-Justified, 18-bit data 0 Reserved 1 Reserved Table 5. Digital Interface Formats - PCM Mode CS4398 REV2 REV1 REV0 - - - DEM0 FM1 FM0 Format Figure (Default ...
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... DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 6. Digital Interface Formats - DSD Mode . Gain -10dB ATAPI4 ATAPI3 CS4398 Description dB T1=50 µs 0dB µ 3.183 kHz 10.61 kHz Figure 17. De-Emphasis Curve 2 1 ATAPI2 ...
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... When set to 0 (default), this function is disabled. 7.3.4 ATAPI Channel Mixing and Muting (ATAPI4:0) Bits 4-0 Default = 01001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4398 implements the channel-mixing functions of the ATAPI CD-ROM specification. Refer to Ta- ble and Figure 18 for additional information. Left Channel Audio Data Right Channel ...
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... MUTE 0 1 MUTE 1 0 MUTE 1 1 MUTE [(aL+bR)/ [(aL+bR)/ [(bL+aR)/ [(aL+bR)/2] CS4398 AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] aL MUTE b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] aL MUTE [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] DS568F1 ...
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... The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default), this function is disabled. DS568F1 MUTE_A MUTE_B CS4398 Reserved MUTEP1 MUTEP0 ...
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... Table 7 are approximate. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. Binary Code VOL4 VOL3 Decimal Value 00000000 0 00000001 1 00000110 6 11111111 255 Table 7. Example Digital Volume Settings CS4398 VOL2 VOL1 VOL0 Volume Setting 0 dB -0.5 dB -3.0 dB -127.5 dB DS568F1 ...
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... The zero cross function is independently monitored and implemented for each channel. DS568F1 RMP_DN Reserved PCM Description Immediate Change Zero Cross Soft Ramp Soft Ramp on Zero Crossings CS4398 FILT_SEL Reserved DIR_DSD DSD Description Immediate Change Soft Ramp 35 ...
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... When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion. In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available (see Section 2 for filter specifications). 36 CS4398 DS568F1 ...
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... Master Clock Divide-by-3 ENABLE (MCLKDIV3) Bit 3 Function: When set to 1, the MCLKDIV bit enables a circuit that divides the externally applied MCLK signal by 3 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged. DS568F1 MCLKDIV2 MCLKDIV3 CS4398 Reserved Reserved Reserved ...
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... DSD Phase Modulation Mode Enable (DSD_PM_EN) Bit 0 Function: When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode CS4398 1 0 DSD_PM_MODE DSD_PM_EN 0 0 DS568F1 ...
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... The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1. CDB4398 Evaluation Board Datasheet 2. “Design Notes for a 2-Pole Filter with Differential Input”. Cirrus Logic Application Note AN48 3. The I²C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com “ DS568F1 CS4398 39 ...
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... BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. Symbol 28-TSSOP θ JA θ JC CS4398 1 E1 ∝ END VIEW L Millimeters Note NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 1 6 ...
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... Figure 23. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 25. Single-Speed (slow) Transition Band CS4398 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0 ...
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... Figure 29. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 31. Double-Speed (fast) Passband Ripple CS4398 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...
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... Figure 35. Double-Speed (slow) Passband Ripple 100 120 0.7 0.8 0.9 1 0.2 Figure 37. Quad-Speed (fast) Transition Band CS4398 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...
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... Figure 41. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 43. Quad-Speed (slow) Passband Ripple CS4398 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...
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... May 2005 -Removed -CZ ordering option (PCN_0044 dated Jan. 2005) -Improved Interchannel Isolation specification -Updated analog output impedance -Corrected Ramp_UP and Ramp_DN bit descriptions -Updated legal text F1 July 2005 -Changed datasheet status to Final -Updated legal text DS568F1 Changes Table 8. Revision Table CS4398 45 ...
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... FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. 46 CS4398 DS568F1 ...