AD5664RBRMZ-3 Analog Devices Inc, AD5664RBRMZ-3 Datasheet - Page 21

• Manufacturer Part Number: AD5664RBRMZ-3
• Description: IC DAC NANO 16BIT 1.25V 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5664RBRMZ-3

• Data Interface: Serial
• Settling Time: 4µs
• Number Of Bits: 16
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.6mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 16bit
• Sampling Rate: 220kSPS
• Input Channel Type: Serial
• Supply Current: 950µA
• Digital Ic Case Style: SOP
• No. Of Pins: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5664REBZ - BOARD EVALUATION FOR AD5664R
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

At this stage, the SYNC line can be kept low or be brought high. In
either case, it must be brought high for a minimum of 15 ns before
the next write sequence so that a falling edge of SYNC can initiate
the next write sequence.
Because the SYNC buffer draws more current when V
than it does when V
between write sequences for even lower power operation. As
mentioned previously, it must, however, be brought high again
just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t care bits. The next three are the command
bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address,
A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word.
The data-word comprises the 16-, 14-, 12-bit input code
followed by 0, 2, or 4 don’t care bits, for the AD5664R,
AD5644R, and AD5624R, respectively (see Figure 52, Figure 53,
and Figure 54). These data bits are transferred to the DAC
register on the 24
SCLK
SYNC
DIN
DB23 (MSB)
DB23 (MSB)
DB23 (MSB)
X
X
X
th
SYNC HIGH BEFORE 24
X
X
X
falling edge of SCLK.
IN
DB23
COMMAND BITS
COMMAND BITS
COMMAND BITS
= 0.8 V, SYNC should be idled low
C2
C2
C2
INVALID WRITE SEQUENCE:
C1
C1
C1
C0
C0
C0
TH
ADDRESS BITS
ADDRESS BITS
ADDRESS BITS
A2
A2
A2
FALLING EDGE
A1
A1
A1
DB0
A0
A0
A0
Figure 52. AD5664R Input Shift Register Contents
Figure 53. AD5644R Input Shift Register Contents
Figure 54. AD5624R Input Shift Register Contents
D13
D15
D11
IN
D14
D12
D10
Figure 55. SYNC Interrupt Facility
= 2 V
D13
D11
D9
Rev. B | Page 21 of 28
D10
D12
D8
D11
D9
D7
DATA BITS
D10
DATA BITS
D8
D6
Table 8. Command Definition
C2
0
0
0
0
1
1
1
1
Table 9. Address Command
A2
0
0
0
0
1
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least
24 falling edges of SCLK, and the DAC is updated on the 24
falling edge. However, if SYNC is brought high before the 24
falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
D9
D7
D5
C1
0
0
1
1
0
0
1
1
A1
0
0
1
1
1
VALID WRITE SEQUENCE, OUTPUT UPDATES
D8
D6
D4
DATA BITS
DB23
ON THE 24
C0
0
1
0
1
0
1
0
1
A0
0
1
0
1
1
D7
D5
D3
AD5624R/AD5644R/AD5664R
D6
D4
D2
Command
Write to input register n
Update DAC register n
Write to input register n, update all
(software LDAC)
Write to and update DAC channel n
Power down DAC (power-up)
Reset
LDAC register setup
Internal reference setup (on/off )
Address (n)
DAC A
DAC B
DAC C
DAC D
All DACs
TH
FALLING EDGE
D5
D3
D1
D2
D4
D0
DB0
D3
D1
X
D0
D2
X
Figure 55
D1
DB0 (LSB)
DB0 (LSB)
DB0 (LSB)
X
X
D0
X
X
).
th
th