MCP4812-E/P Microchip Technology, MCP4812-E/P Datasheet - Page 25

• Manufacturer Part Number: MCP4812-E/P
• Description: DAC 10BIT DUAL SPI/VREF 8PDIP
• Manufacturer: Microchip Technology

Specifications of MCP4812-E/P

• Number Of Converters: 2
• Settling Time: 4.5µs
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Bits: 10
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Number Of Dac Outputs: 2
• Resolution: 10 bit
• Interface Type: SPI
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 55 C
• Supply Current: 415 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
The MCP4802/4812/4822 family of devices are
general purpose DACs for various applications where
a precision operation with low-power and internal
voltage reference is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor Calibration
• Precision Selectable Voltage Reference
• Portable Instrumentation (Battery-Powered)
• Calibration of Optical Communication Devices
6.1
The MCP4802/4812/4822 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup
and input codes from the digital devices. The serial
protocol can be interfaced to SPI or Microwire
peripherals that is common on many microcontroller
units (MCUs), including Microchip’s PIC
dsPIC
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the two DAC
outputs. By bringing down the LDAC pin to “low”, all
DAC input codes and settings in the two DAC input reg-
isters are latched into their DAC output registers at the
same time. Therefore, both DAC
are updated at the same time.
example of the pin connections. Note that the LDAC pin
can be tied low (V
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16 clock transmission has been received and the CS
pin has been raised.
6.2
The typical application will require a bypass capacitor
in order to filter out the noise in the power supply
traces. The noise can be induced onto the power
supply's traces from various events such as digital
switching or as a result of changes on the DAC's
output. The bypass capacitor helps to minimize the
effect of these noise sources.
appropriate bypass strategy. In this example, two
bypass capacitors are used in parallel: (a) 0.1 µF
(ceramic) and (b)10 µF (tantalum). These capacitors
should be placed as close to the device power pin
(V
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
 2010 Microchip Technology Inc.
SS
DD
of the device should reside on the analog plane.
) as possible (within 4 mm).
®
DSCs.
TYPICAL APPLICATIONS
Digital Interface
Power Supply Considerations
SS
) to reduce the required
Figure 6-1
Figure 6-1
A
and DAC
®
illustrates an
MCUs and
shows an
B
outputs
DD
and
6.3
The voltage noise density (in µV/Hz) is illustrated in
Figure
primarily a result of the internal reference voltage.
Its 1/f corner (f
Figure 2-14
mV
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypass capacitor sized to produce a 1 kHz LPF would
result in an E
necessary when trying to achieve the low DNL error
performance (at G = 1) that the MCP4802/4812/4822
devices are capable of. The tested range for stability is
.001µF through 4.7 µF.
FIGURE 6-1:
Diagram.
6.4
Inductively-coupled AC transients and digital switching
noises can degrade the output signal integrity, and
potentially reduce the device performance. Careful
board layout will minimize these effects and increase
the Signal-to-Noise Ratio (SNR). Bench testing has
shown
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
C2 = 0.1 µF
C1 = 10 µF
1 µF
V
V
MCP4802/4812/4822
OUTA
OUTB
P-P
C1
). A small bypass capacitor on V
2-13. This noise appears at V
V
Output Noise Considerations
Layout Considerations
that
AV
DD
illustrates the voltage noise (in mV
SS
NREF
CORNER
C2
a
SDI
1 µF
V
V
of about 100 µV
OUTA
OUTB
C1
multi-layer
) is approximately 400 Hz.
Typical Connection
V
AV
DD
SS
C2
SDI
board
RMS
LDAC
DS22249A-page 25
CS
. This would be
SDO
SCK
CS
OUTX
C1
0
OUTX
utilizing
1
V
, and is
V
DD
RMS
SS
is an
C2
or
a