AD9716BCPZ Analog Devices Inc, AD9716BCPZ Datasheet - Page 38

• Manufacturer Part Number: AD9716BCPZ
• Description: IC DAC DUAL 12BIT LO PWR 40LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9716BCPZ

• Data Interface: Serial
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 86mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel, Serial
• Supply Current: 11mA
• Digital Ic Case Style: CSP
• No. Of Pins: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9714/AD9715/AD9716/AD9717
Register
AUXDAC I
AUX CTLI
Reference
Resistor
Cal Control
Cal Memory
Memory Address
Memory Data
Address
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Bit
7:0
7
6:5
4:2
1:0
5:0
7
6
5
4
3
2:0
7
6
3:2
1:0
5:0
5:0
Name
IAUXDAC[7:0]
IAUXEN
IAUXRNG[1:0]
IAUXOFS[2:0]
IAUXDAC[9:8]
RREF[5:0]
PRELDQ
PRELDI
CALSELQ
CALSELI
CALCLK
DIVSEL[2:0]
CALSTATQ
CALSTATI
CALMEMQ[1:0]
CALMEMI[1:0]
MEMADDR[5:0]
MEMDATA[5:0]
Description
AUXDAC I output voltage adjustment word LSBs.
0x3FF: sets AUXDAC I output to full scale.
0x200: sets AUXDAC I output to midscale.
0x000 (default): sets AUXDAC I output to bottom of scale.
0 (default): AUXDAC I output disabled.
1: enables AUXDAC I output.
00 (default): sets AUXDAC I output voltage range to 2 V.
01: sets AUXDAC I output voltage range to 1.5 V.
10: sets AUXDAC I output voltage range to 1.0 V.
11: sets AUXDAC I output voltage range to 0.5 V.
000 (default): sets AUXDAC I top of range to 1.0 V.
001: sets AUXDAC I top of range to 1.5 V.
010: sets AUXDAC I top of range to 2.0 V.
011: sets AUXDAC I top of range to 2.5 V.
100: sets AUXDAC I top of range to 2.9 V.
AUXDAC I output voltage adjustment word MSBs (default = 00).
Permits an adjustment of the on-chip reference voltage and output at REFIO (see
Figure 98) twos complement.
000000 (default): sets the value of R
011111: sets the value of R
100000: sets the value of R
111111: sets the value of R
0 (default): preload Q DAC calibration reference set to 32.
1: preload Q DAC calibration reference set by user (Cal Address 1).
0 (default): preload I DAC calibration reference set to 32.
1: preload I DAC calibration reference set by user (Cal Address 1).
0 (default): Q DAC self-calibration done.
1: select Q DAC self-calibration.
0 (default): I DAC self-calibration done.
1: select I DAC self-calibration.
0 (default): calibration clock disabled.
1: calibration clock enabled.
Calibration clock divide ratio from DAC clock rate.
000 (default): divide by 256.
001: divide by 128.
…
110: divide by 4.
111: divide by 2.
0 (default): Q DAC calibration in progress.
1: calibration of Q DAC complete.
0 (default): I DAC calibration in progress.
1: calibration of I DAC complete.
Status of Q DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user calibrated.
Status of I DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user calibrated.
Address of static memory to be accessed.
Data for static memory access.
Rev. A | Page 38 of 80
REF
REF
REF
to 12 kΩ, V
to 8 kΩ, V
to 10 kΩ, V
REF
to 10 kΩ, V
REF
REF
REF
= 0.8 V.
= 1.2 V.
= 1.0 V.
REF
= 1.0 V.