MAX517AESA+ Maxim Integrated Products, MAX517AESA+ Datasheet - Page 11

• Manufacturer Part Number: MAX517AESA+
• Description: IC DAC 8BIT SGL 2WIRE SER 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX517AESA+

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: I²C, Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 696mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Dac Outputs: 1
• Resolution: 8 bit
• Interface Type: Serial (I2C)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 1.5 mA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Furthermore if the transmission’s last command byte
has PD high, the output latches are updated, but volt-
age outputs will not reflect the newly entered data
because the DAC enters power-down mode when the
STOP condition is detected. When in power-down, the
DAC outputs float. In this mode, the supply current is a
maximum of 20µA. A command byte with the PD bit low
returns the MAX517/MAX518/MAX519 to normal opera-
tion following a STOP condition, with the voltage out-
puts reflecting the output-latch contents (Figures 10a
and 10b). Because each subsequent command byte
overwrites the previous PD bit, only the last command
byte of a transmission affects the power-down state.
Setting the RST bit high clears the DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 11a). If a reset is issued, the
Figure 10. Returning to Normal Operation from Power-Down
Figure 11. Resetting DAC Outputs
(a)
(b)
SDA
CONDITION
CONDITION
SDA
START
START
NOTE: X = DON'T CARE
(a)
(b)
SDA
CONDITION
CONDITION
SDA
START
START
NOTE: X = DON'T CARE
0
0
1
1
ADDRESS BYTE
ADDRESS BYTE
0
0
0
0
AD3
AD3
or
or
1
1
______________________________________________________________________________________
1
1
AD2 AD1AD0 0 0
AD2 AD1 AD0 0 0 0
ADDRESS BYTE
ADDRESS BYTE
or
or
1
1
0
0
AD3
AD3
or
1
or
1
AD2 AD1 AD0 0
AD2 AD1 AD0 0
1
or
or
1
ACK
ACK
0 0 0 1 0
ACK
0
ACK
0
0
COMMAND BYTE
COMMAND BYTE
0
0
0 0 0 0 0
(RST)
(RST)
1
(
0
ALL INPUT LATCHES
(ADDRESSING DAC0)
COMMAND BYTE
0
COMMAND BYTE
0
SET TO 0.
2-Wire Serial 8-Bit DACs with
X X X
X X X
0
(
(PD)
(PD)
ALL INPUT LATCHES
0
SET TO 0.
X X X
X X
ACK
ACK
0
0
)
(
STOP
CONDITION
X X X X X X X X
ALL OUTPUTS
SET TO 0.
0
CONDITION
ACK
ACK
0
0
STOP
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 11b).
All changes made during a transmission affect the
MAX517/MAX518/MAX519’s outputs only when the
transmission ends and a STOP has been recognized.
The R0, R1, and R2 bits are reserved and must be set
to zero.
The MAX517/MAX518/MAX519 are fully compatible
with existing I
impedance inputs; SDA has an open drain that pulls
the data line low during the 9th clock pulse. Figure 12
shows a typical I
)
OUTPUT BYTE
0
"DUMMY"
0
)
(
OUTPUT BYTE
0
DEVICE RETURNS TO
NORMAL OPERATION
(SET TO 0)
Rail-to-Rail Outputs
0
(
0
DAC0 INPUT
LATCH SET TO 0.
0
ACK
2
0
C systems. SCL and SDA are high-
2
0
OUTPUT BYTE PAIRS
C application.
COMMAND BYTE/
0
ADDITIONAL
)
ACK
0
)
(
STOP
CONDITION
DEVICE RETURNS TO NORMAL OPERATION.
DAC0 SET TO 0.
(
DAC OUTPUTS SET TO 0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS.
STOP
CONDITION
I
2
C Compatibility
)
11
)