MX7837KR+ Maxim Integrated Products, MX7837KR+ Datasheet - Page 6

• Manufacturer Part Number: MX7837KR+
• Description: IC DAC 12BIT DL MULT 24SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MX7837KR+

• Settling Time: 4µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1 shows a simplified circuit diagram for one of
the DACs and the output amplifier. Using a segmented
scheme, the two MSBs of the 12-bit data word are
decoded to drive the three switches (A to C). The
remaining 10 bits drive the switches (S0 to S9) in a
standard R-2R ladder.
Each switch (A to C) directs 1/4 of the total reference
current, and the remaining current passes through the
R-2R section.
The output amplifier and feedback resistor convert cur-
rent to voltage as follows: V
is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The output amplifier is capable of developing ±10V
across a 2kΩ load. It is internally compensated and
settles to 0.01% FSR (1/2LSB) in less than 4µs. V
on the MX7837 is not internally connected to R
Complete, Dual, 12-Bit
Multiplying DACs
Figure 1. D/A Simplified Circuit Diagram
Figure 2. MX7847 Input Control Logic
6
_______________Detailed Description
V
_______________________________________________________________________________________
C
REF
2R
CSA
CSB
B
2R
WR
A
2R
R
SHOWN FOR ALL 1s ON DAC
S9
2R
R
S8
OUT_
2R
R
= (-D)(V
DAC A LATCH
DAC B LATCH
2R
S0
D/A Section
REF_
2R
), where D
R/
FB
2
AGND
.
V
OUT
OUT
Figure 2 shows the MX7847 input control logic. The
device contains two independent DACs, each with its
own CS input and a common WR input. CSA and WR
control data loading to the DAC A latch, and CSB and
WR control data loading to the DAC B latch. The latch-
es are edge triggered so that input data is latched to
the respective latch on WR's rising edge. The same
data will be latched to both DACs if CSA and CSB are
low and WR is taken high. Table 1 shows the device
control-logic truth table, and Figure 3 shows the write-
cycle timing diagram.
Table 1. MX7847 Truth Table
X = Don't Care
The MX7837 input loading structure is configured for
interfacing with 8-bit-wide data-bus microprocessors.
Each DAC has two 12-bit latches: an input latch, and a
DAC latch. Each input latch is subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch.
The data held in the DAC latches determines the out-
puts. Figure 4 shows the MX7837 input control logic,
and Figure 5 shows the write-cycle timing diagram.
Figure 3. MX7847 Write-Cycle Timing Diagram
CSA
CSA, CSB
X
1
0
1
0
1
DATA
WR
CSB
X
1
1
0
0
1
WR
t
1
1
X
0
0
0
= Rising Edge Triggered
Interface Logic Information
Interface Logic Information
No Data Transfer
No Data Transfer
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
VALID DATA
t
3
t
4
Function
t
2
t
5
(MX7847)
(MX7837)