MCP4802-E/SN Microchip Technology, MCP4802-E/SN Datasheet - Page 21

• Manufacturer Part Number: MCP4802-E/SN
• Description: DAC 8BIT DUAL SPI/VREF 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4802-E/SN

• Number Of Converters: 2
• Settling Time: 4.5µs
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Bits: 8
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Dac Outputs: 2
• Resolution: 8 bit
• Interface Type: SPI
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Supply Current: 415 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
5.1
The MCP4802/4812/4822 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, available on many microcontrollers, and
supports Mode 0,0 and Mode 1,1. Commands and data
are sent to the device via the SDI pin, with data being
clocked-in
communications are unidirectional and, thus, data
cannot be read out of the MCP4802/4812/4822
devices. The CS pin must be held low for the duration
of a write command. The write command consists of
16 bits and is used to configure the DAC’s control and
data latches.
input register that is used to configure and load the
DAC
to
Refer to
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
 2010 Microchip Technology Inc.
Figure 5-3
A
and DAC
SERIAL INTERFACE
Overview
Figure 1-1
on
show the write command for each device.
Register 5-1
B
the
registers for each device.
and SPI Timing Specifications
rising
to
edge
Register 5-3
of
SCK.
Figure 5-1
detail the
The
5.2
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the selected DAC’s input registers.
The MCP4802/4812/4822 devices utilize a double-
buffered latch structure to allow both DAC
DAC
if desired.
By bringing down the LDAC pin to a low state, the con-
tents stored in the DAC’s input registers are transferred
into the DAC’s output registers (V
and V
All writes to the MCP4802/4812/4822 devices are
16-bit words. Any clocks after the first 16
ignored.
Configuration bits. The remaining 12 bits are data bits.
No data can be transferred into the device with CS
high. The data transfer will only occur if 16 clocks have
been transferred into the device. If the rising edge of
CS occurs prior, shifting of data into the input registers
will be aborted.
MCP4802/4812/4822
B
OUTB
’s outputs to be synchronized with the LDAC pin,
Write Command
The
are updated at the same time.
Most
Significant
OUT
DS22249A-page 21
), and both V
four
th
clock will be
bits
A
’s and
OUTA
are