AD5662BRMZ-1 Analog Devices Inc, AD5662BRMZ-1 Datasheet - Page 15

• Manufacturer Part Number: AD5662BRMZ-1
• Description: IC DAC 16BIT BUFF V-OUT 8MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5662BRMZ-1

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: 4 mA to 20 mA Process Control Loop Using AD5662 (CN0009) 16-Bit Fully Isolated Voltage Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0063) 16-Bit Fully Isolated 4 mA to 20 mA Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0064)
• Settling Time: 8µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 750µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resolution (bits): 16bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 2.7V To 5.5V
• Supply Current: 150µA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 34). The first
six bits are don’t cares. The next two are control bits that control
the part’s mode of operation (normal mode or any one of three
power-down modes). See the Power-Down Modes section for a
more complete description of the various modes. The next 16
bits are the data bits. These are transferred to the DAC register
on the 24
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24
th
falling edge. However, if SYNC is brought high before the
SCLK
SYNC
DB23 (MSB)
DIN
X
th
falling edge of SCLK.
X
SYNC HIGH BEFORE 24
X
DB23
INVALID WRITE SEQUENCE:
X
X
X
TH
FALLING EDGE
PD1
DB0
PD0
D15
0
0
1
1
D14
Figure 34. Input Register Contents
Figure 35. SYNC Interrupt Facility
0
1
0
1
NORMAL OPERATION
D13
1 kΩ TO GND
100 kΩ TO GND
THREE-STATE
Rev. A | Page 15 of 24
D12
D11
24
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
POWER-ON RESET
The AD5662 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5662x-1
DAC output powers up to 0 V, and the AD5662x-2 DAC output
powers up to midscale. The output remains there until a valid
write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
POWER-DOWN MODES
D10
th
falling edge, this acts as an interrupt to the write sequence.
VALID WRITE SEQUENCE, OUTPUT UPDATES
D9
DATA BITS
DB23
ON THE 24
D8
D7
TH
FALLING EDGE
D6
D5
DB0
D4
D3
Figure 35
D2
D1
DBO (LSB)
).
AD5662
D0