AD1852JRS Analog Devices Inc, AD1852JRS Datasheet
AD1852JRS
Specifications of AD1852JRS
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AD1852JRS Summary of contents
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FEATURES 5 V Stereo Audio DAC System Accepts 16-Bit/18-Bit/20-Bit/24-Bit Data Supports 24 Bits, 192 kHz Sample Rate Accepts a Wide Range of Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz Multibit ...
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AD1852–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages ( Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO ANALOG PERFORMANCE (See ...
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TEMPERATURE RANGE Specifications Guaranteed Functionality Guaranteed Storage Specifications subject to change without notice. POWER Supplies Voltage, Analog and Digital Analog Current Analog Current—RESET Digital Current Digital Current—RESET Dissipation Operation—Both Supplies Operation—Analog Supply Operation—Digital Supply Power Supply Rejection Ratio 1 kHz ...
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... JC [Junction-to-Case]) Model Temperature AD1852JRS AD1852JRSRL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1852 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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Pin Input/Output Pin Name 1 I DGND 2 I MCLK 3 I CLATCH 4 I CCLK 5 I CDATA 192/ ZEROR 9 I DEEMP 10 I 96/48 11 AGND 12 O OUTR+ ...
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AD1852 L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA LSB MSB INPUT L/RCLK INPUT BCLK INPUT SDATA MSB MSB–1 MSB–2 INPUT L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA MSB MSB–1 MSB–2 LSB+2 INPUT L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA MSB ...
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OPERATING FEATURES Serial Data Input Port The AD1852’s flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The serial mode is set by using either the ...
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AD1852 Chip Mode Allowable Master Clock Frequencies INT8 Mode 256 F , 384 S INT4 Mode 128 F , 192 S INT2 Mode Note that the AD1852 is capable “packed ...
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Table III. SPI Digital Timing t CCLK HI Pulsewidth CCH t CCLK LOW Pulsewidth CCL t CDATA Setup Time CSU t CDATA Hold Time CHD t CLATCH LOW Pulsewidth CLL t CLATCH HI Pulsewidth CLH t CLATCH Setup Time CLSU ...
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AD1852 Bit 11 Bit 10 INT2 Mode INT4 Mode OR’d with Pin 7 OR’d with Pin 10 Bits in Right- (192/48). (96/48). Default = 0 Default = 0 Control Register Table V shows the functions of the control register. The ...
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Figures 9–14 show the calculated frequency response of the digital interpolation filters. Figures 15–26 show the performance of the AD1852 as measured by an Audio Precision System 2 Cascade. For the wideband plots, the noise floor shown in the plots ...
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AD1852 –50 –60 –70 –80 –90 –100 –110 –120 10 100 1k FREQUENCY – Hz Figure 15. THD vs. Frequency Input @ –3 dBFS kHz 2 0 –2 –4 –6 –8 –10 –12 10 100 1k FREQUENCY – ...
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Figure 21. Linearity vs. Amplitude Input 200 Hz kS/s, 24-Bit Word –64 –66 –68 –70 –72 –74 – 100 FREQUENCY – Hz ...
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... AD1852 STEREO DAC DVDD AVDD C3 C2 100nF 100nF DVDD AVDD 96/48 192/48 NC OUTL+ SDATA U1 LRCLK OUTL– AD1852JRS SCLK MCLK OUTR+ IDPM0 IDPM1 OUTR– DEEMP MUTE CLATCH CCLK CDATA ZEROR FILTR ZEROL FILTB RESET DGND AGND AGND FB1 600Z ...
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SDATA LEFT/RIGHT BCLK DATA SEPARATOR AND INVERTER LRCLK MCLK LRCLK INPUT TO DATA SEPARATOR Ln SDATA LRCLK DATA SEPARATOR LSDATA OUTPUT RDATA REV 3.01k L+ SDATA LRCLK 3.01k BCLK ...
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AD1852 0.311 (7.9) 0.301 (7.64) 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08 0.212 (5.38) 0.205 (5.21 ...