AD421BRZ Analog Devices Inc, AD421BRZ Datasheet - Page 3

• Manufacturer Part Number: AD421BRZ
• Description: IC DAC SRL 16BIT 16-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD421BRZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.95mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 125SPS
• Input Channel Type: Serial
• Supply Current: 575µA
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Number Of Channels: 1
• Resolution: 16b
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Delta-Sigma
• Power Supply Requirement: Single
• Output Type: Current
• Single Supply Voltage (min): 2.95V
• Single Supply Voltage (max): 5.05V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. C
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
Guaranteed by characterization at initial product release, not production tested.
See Figures 1 and 2.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CK
CL
CH
DW
DS
DH
LD
LL
LH
input.
CLOCK
LATCH
DATA
CLOCK
LATCH
DATA
Figure 1. Serial Interface Waveforms (Normal Data Load)
(B Versions)
100
50
50
30
30
0
50
50
50
1, 2, 3
1
0
Figure 2. Serial Interface Timing Diagram
1 1
(V
CC
= +3 V to +5 V, T
0 0
CC
) and timed from a voltage level of (V
1
WORD "N"
t
0
C L
t
D S
–3–
0
t
A
D W
1
t
= T
C K
1
MIN
t
1
D H
to T
t
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
C H
0
t
MAX
L D
0
t
LL
unless otherwise noted)
1 1
IN
+ V
IL
)/2; tr and tf should not exceed 1 µs on any digital
t
1
WORD "N +1"
L H
0
0
1
Conditions/Comments
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
AD421