CYS25G0101DX-ATC Cypress Semiconductor Corp, CYS25G0101DX-ATC Datasheet - Page 12

• Manufacturer Part Number: CYS25G0101DX-ATC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYS25G0101DX-ATC

• Number Of Transmitters: 1
• Number Of Receivers: 1
• Power Supply Requirement: Single
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / Rohs Status: Not Compliant

AC Specifications
Table 7. AC Specifications - Parallel Interface
Table 8. AC Specifications - REFCLK
Table 9. AC Specifications–CML Serial Outputs
Table 10. Jitter Specifications
Document Number: 38-02009 Rev. *L
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
TS
TXCLKI
TXCLKID
TXCLKIR
TXCLKIF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD
TXCLKOR
TXCLKOF
RS
RXCLK
RXCLKD
RXCLKR
RXCLKF
RXDS
RXDH
RXPD
REF
REFP
REFD
REFT
REFR
REFF
RISE
FALL
TJ-TXPLL
TJ-RXPLL
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in
8. +20 ppm is required to meet the SONET output frequency specification.
9. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter.
10. Typical values are measured at room temperature and the Max values are measured at 0° C.
11. This device passes the Bellcore specification from -10° C to 85° C.
Parameter
Parameter
Parameter
Parameter
TXCLKI Frequency (must be frequency coherent to REFCLK)
TXCLKI Period
TXCLKI Duty Cycle
TXCLKi Rise Time
TXCLKi Fall Time
Write Data Setup to ↑ of TXCLKI
Write Data Hold from ↑ of TXCLKI
TXCLKO Frequency
TXCLKO Period
TXCLKO Duty Cycle
TXCLKO Rise Time
TXCLKO Fall Time
RXCLK Frequency
RXCLK Period
RXCLK Duty Cycle
RXCLK Rise Time
RXCLK Fall Time
Recovered Data Setup with reference to ↑ of RXCLK
Recovered Data Hold with reference to ↑ of RXCLK
Valid Propagation Delay
REFCLK Input Frequency
REFCLK Period
REFCLK Duty Cycle
REFCLK Frequency Tolerance — (relative to received serial data)
REFCLK Rise Time
REFCLK Fall Time
CML Output Rise Time (20–80%, 100Ω balanced load)
CML Output Fall Time (80–20%, 100Ω balanced load)
Total Output Jitter for TX PLL (p-p)
Total Output Jitter for TX PLL (rms)
Total Output Jitter for RX CDR PLL (p-p)
Total Output Jitter for RX CDR PLL (rms)
[6]
[6]
[7]
Description
Description
Description
Description
[9]
[9, 11]
[9]
[9, 11]
Figure
8.
[8]
154.5
154.5
154.5
154.5
–100
Min
6.38
Min
Min
6.38
6.38
6.38
–1.0
Min
0.3
0.3
60
60
0.3
0.3
1.5
0.5
0.3
0.3
0.3
0.3
2.2
2.2
35
40
43
43
CYS25G0101DX
Typ
0.007
0.035
0.008
156.5
0.03
156.5
156.5
156.5
+100
Max
6.47
Max
6.47
6.47
6.47
Typ
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
65
57
60
57
[10]
Max
0.008
0.04
0.05
0.01
Max
Page 12 of 18
170
170
Unit
MHz
ppm
Unit
MHz
MHz
MHz
[10]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
Unit
Unit
ps
ps
UI
UI
UI
UI
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