ADMCF328BRZ Analog Devices Inc, ADMCF328BRZ Datasheet - Page 22

• Manufacturer Part Number: ADMCF328BRZ
• Manufacturer: Analog Devices Inc

Specifications of ADMCF328BRZ

• Operating Current: 123mA
• Operating Temperature Classification: Industrial
• Package Type: SOIC W
• Operating Supply Voltage (min): -0.3V
• Operating Supply Voltage (max): 7V
• Lead Free Status / Rohs Status: Compliant

ADMCF328
The functionality of the PIO6/CLKOUT, PIO7/AUX1, and
PIO8/AUX0 pins may be selected on a pin-by-pin basis as desired.
PIO Registers
The configuration of all registers of the PIO system is shown at
the end of the data sheet.
INTERRUPT CONTROL
The ADMCF328 can respond to 16 different interrupt sources,
some of which are generated by internal DSP core interrupts
and others from the motor control peripherals. The DSP core
interrupts include the following:
• A Peripheral (or IRQ2) Interrupt.
• A SPORT1 Receive (or IRQ0) and a SPORT1 Transmit (or
• Two Software Interrupts.
• An Interval Timer Time-Out Interrupt.
The interrupts generated by the motor control peripherals include:
• A PWMSYNC Interrupt.
• Nine Programmable Input/Output (PIO) Interrupts.
• A PWM Trip Interrupt.
The core interrupts are internally prioritized and individually
maskable. All peripheral interrupts are multiplexed into the DSP
core through the peripheral (IRQ2) interrupt.
The PWMSYNC interrupt is triggered by a low-to-high tran-
sition on the PWMSYNC pulse. The PWMTRIP interrupt is
triggered on a high-to-low transition on the PWMTRIP pin, an
overcurrent on the I
Register. A PIO interrupt is detected on any change of state
(high-to-low or low-to-high) on the PIO lines.
The ADMCF328 interrupt control system is configured and
controlled by the IFC, IMASK, and ICNTL registers of the
DSP core and by the IRQFLAG register for the PWMSYNC
and PWMTRIP interrupts. PIO interrupts are enabled and
disabled by the PIOINTEN0 and PIOINTEN1 Registers.
Interrupt Source
PWMTRIP
Peripheral Interrupt (IRQ2)
PWMSYNC
PIO
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit Interrupt (or IRQ1) 0x0020
SPORT1 Receive Interrupt (or IRQ0) 0x0024
Timer
Interrupt Masking
Interrupt masking (or disabling) is controlled by the IMASK
Register of the DSP core. This register contains individual bits
that must be set to enable the various interrupt sources. If any
peripheral interrupt (PWMSYNC, PWMTRIP, or PIO) is to be
enabled, the IRQ2 interrupt Enable Bit (Bit 9) of the IMASK
Register must be set. The configuration of the IMASK Register
of the ADMCF328 is shown at the end of the data sheet.
IRQ1) Interrupt
Table IX. Interrupt Vector Addresses
SENSE
pin, or by writing to the PWMSWT
Interrupt Vector Address
0x002C (Highest Priority)
0x0004
0x000C
0x0008
0x0018
0x001C
0x0028 (Lowest Priority)
–22–
Interrupt Configuration
The IFC and ICNTL Registers of the DSP core control and config-
ure the interrupt controller of the DSP core. The IFC Register is a
16-bit register that may be used to force and/or clear any of
the eight DSP interrupts. Bits 0 to 7 of the IFC Register may
be used to clear the DSP interrupts while Bits 8 to 15 can be
used to force a corresponding interrupt. Writing to Bits 11 and 12
in IFC is the only way to create the two software interrupts.
The ICNTL register is used to configure the sensitivity (edge
or level) of the IRQ0, IRQ1, and IRQ2 interrupts and to enable/
disable interrupt nesting. Setting Bit 0 of ICNTL configures the
IRQ0 as edge-sensitive, while clearing the bit configures it as
level-sensitive. Bit 1 is used to configure the IRQ1 interrupt.
Bit 2 is used to configure the IRQ2 interrupt. It is recommended
that the IRQ2 interrupt always be configured as level-sensitive
to ensure that no peripheral interrupts are lost. Setting Bit 4 of
the ICNTL register enables interrupt nesting. The configuration
of both the IFC and ICNTL registers is shown at the end of the
data sheet.
Interrupt Operation
Following a reset, the ROM code on the ADMCF328 must
copy a default interrupt vector table into program memory
RAM from address 0x0000 to 0x002F. Since each interrupt
source has a dedicated four-word space in this vector table, it is
possible to code short interrupt service routines (ISR) in place.
Alternatively, it may be necessary to insert a JUMP instruction
to the appropriate start address of the interrupt service routine if
more memory is required for the ISR.
When an interrupt occurs, the program sequencer ensures that
there is no latency (beyond synchronization delay) when pro-
cessing unmasked interrupts. In the case of the timer, SPORT1,
and software interrupts, the interrupt controller automatically
jumps to the appropriate location in the interrupt vector table. At
this point, a JUMP instruction to the appropriate ISR is required.
Motor control peripheral interrupts are slightly different. When a
peripheral interrupt is detected, a bit is set in the IRQFLAG Regis-
ter for PWMSYNC and PWMTRIP or in the PIOFLAG0, or
PIOFLAG1 registers for a PIO interrupt, and the IRQ2 line
is pulled low until all pending interrupts are acknowledged.
The DSP software must determine the source of the interrupts
by reading IRQFLAG register. If more than one interrupt
occurs simultaneously, the higher priority interrupt service routine
is executed. Reading the IRQFLAG register clears the PWMTRIP
and PWMSYNC bits and acknowledges the interrupt, thus allow-
ing further interrupts when the ISR exits.
A user’s PIO interrupt service routine must read the PIOFLAG0
and PIOFLAG1 registers to determine which PIO port is
the source of the interrupt. Reading registers PIOFLAG0 and
PIOFLAG1 clears all bits in the registers and acknowledges
the interrupt, thus allowing further interrupts after the ISR exits.
The configuration of all these registers is shown at the end of
the data sheet.
REV. A