CY8C5387AXI-108 Cypress Semiconductor Corp, CY8C5387AXI-108 Datasheet - Page 20

• Manufacturer Part Number: CY8C5387AXI-108
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5387AXI-108

• Lead Free Status / Rohs Status: Compliant

6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external compo-
nents and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Phase-Locked
The IMO provides clock outputs at 3, 6, 12, 24, 48, and 74 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be multi-
plied to higher frequencies. This is a tradeoff between higher
clock frequency and accuracy and, higher power consumption
and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
Document Number: 001-55035 Rev. *F
Loop)
7
12-48 MHz
3-74 MHz
Doubler
IMO
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
4-33 MHz
ECO
24-80 MHz
PRELIMINARY
PLL
Figure 6-1. Clocking Subsystem
External IO
0-66 MHz
or DSI
Clock Mux
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
System
32 kHz ECO
outputs clock frequencies in the range of 24 to 80 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
6.1.1.4 Internal Low Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic inter-
PSoC
®
1,33,100 kHz
5: CY8C53 Family Data Sheet
ILO
7
CPU Clock Divider
Bus Clock Divider
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
4 bit
16 bit
w
w
w
w
s
k
e
s
k
e
s
k
e
s
k
e
Clock
CPU
Clock
Bus
Page 20 of 97
[+] Feedback