AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet
AD9779ABSVZ
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AD9779ABSVZ Summary of contents
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FEATURES Low power: 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 7 dBc @ 80 MHz IF Analog output: adjustable 8 31.7 mA Ω to ...
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AD9776A/AD9778A/AD9779A TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 Digital ...
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DELAY SYNC_O LINE SYNC_I DELAY DATACLK LINE DATA ASSEMBLER I P1D<15:0> LATCH 2× Q LATCH 2× P2D<15:0> PERIPHERAL INTERFACE AD9779A FUNCTIONAL BLOCK DIAGRAM CLOCK GENERATION/DISTRIBUTION 2× 2× × /8 DAC ... 7 2× ...
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AD9776A/AD9778A/AD9779A SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ...
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DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless ...
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AD9776A/AD9778A/AD9779A DIGITAL INPUT DATA TIMING SPECIFICATIONS All modes, −40°C to +85°C. Table 3. Parameter Conditions 1 Input Data Setup Time Input data to DATACLK Hold Time Input data to DATACLK Setup Time Input data to REFCLK Hold Time Input data ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect To AVDD33, DVDD33 AGND, DGND, CGND DVDD18, CVDD18 AGND, DGND, CGND AGND DGND, CGND DGND AGND, CGND CGND AGND, DGND I120, VREF, IPTAT AGND OUT1_P, OUT1_N, AGND OUT2_P, OUT2_N, AUX1_P, AUX1_N, AUX2_P, ...
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AD9776A/AD9778A/AD9779A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND ...
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Pin No. Mnemonic Description 39 TXENABLE Transmit Enable. In single port mode, this pin also functions as IQSELECT. 40 P2D<11> Port 2, Data Input D11 (MSB). 41 P2D<10> Port 2, Data Input D10. 42 P2D<9> Port 2, Data Input D9. ...
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AD9776A/AD9778A/AD9779A 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 ...
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Pin No. Mnemonic Description 42 P2D<11> Port 2, Data Input D11. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Ground. 45 P2D<10> Port 2, Data Input D10. 46 P2D<9> Port 2, Data Input D9. 47 P2D<8> Port 2, Data ...
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AD9776A/AD9778A/AD9779A 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 ...
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Pin No. Mnemonic Description 42 P2D<13> Port 2, Data Input D13. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Ground. 45 P2D<12> Port 2, Data Input D12. 46 P2D<11> Port 2, Data Input D11. 47 P2D<10> Port 2, Data ...
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AD9776A/AD9778A/AD9779A TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 –5 –6 0 10k 20k 30k 40k CODE Figure 6. AD9779A Typical INL 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 10k 20k 30k 40k CODE ...
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DATA 200MSPS DATA DATA (MHz) OUT Figure 12. AD9779A Out-of-Band SFDR vs. f 2× Interpolation 100 150MSPS DATA 70 ...
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AD9776A/AD9778A/AD9779A 100 f = 160MSPS DATA 250MSPS 80 DATA (MHz) OUT Figure 18. AD9779A Third-Order IMD vs. f 1× Interpolation 100 f = 160MSPS DATA ...
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OUT Figure 24. AD9779A IMD Performance vs. Digital Full-Scale Input over Output Frequency, 4× Interpolation, f 100 ...
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AD9776A/AD9778A/AD9779A –150 –154 f = 200MSPS DAC –158 f DAC –162 f = 800MSPS DAC –166 –170 (MHz) OUT Figure 30. AD9779A Noise Spectral Density vs. f with a Single Tone Input at −6 dBFS ...
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CODE Figure 36. AD9778A Typical INL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 10k 12k CODE Figure 37. AD9778A Typical DNL 100 ...
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AD9776A/AD9778A/AD9779A –150 –154 f = 200MSPS DAC –158 f DAC –162 f = 800MSPS DAC –166 –170 (MHz) OUT Figure 42. AD9778A Noise Spectral Density vs. f with 500 kHz Spacing 200 MSPS ...
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ADJ CHAN –70 3RD ADJ CHAN –75 –80 2ND ADJ CHAN –85 – 100 125 150 F (MHz) OUT Figure 48. AD9776A ACLR 122.88 MSPS, 4× Interpolation, DATA f /4 ...
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AD9776A/AD9778A/AD9779A TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure ...
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THEORY OF OPERATION The AD9776A/AD9778A/AD9779A have many features that make them highly suited for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband ...
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AD9776A/AD9778A/AD9779A SERIAL PERIPHERAL INTERFACE The SPI port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro- controllers and microprocessors. The port is compatible with most synchronous transfer formats including both the Motorola SPI and Intel® ...
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SERIAL INTERFACE PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device as well as running the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered ...
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AD9776A/AD9778A/AD9779A SPI REGISTER MAP Note that all unused register bits should be kept at the device default values. Table 13. Address Register Name Hex Decimal Bit 7 Comm 0x00 00 SDIO Bidirectional Digital 0x01 01 Interpolation Factor<1:0> Control 0x02 02 ...
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Table 14. SPI Register Description Register Register Name Address Bits Comm 0x00 7 0x00 6 0x00 5 0x00 4 0x00 3 0x00 1 Digital Control 0x01 7:6 0x01 5:2 0x01 1 0x01 0 0x02 7 0x02 6 0x02 5 0x02 ...
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AD9776A/AD9778A/AD9779A Register Register Name Address Bits Sync Control 0x03 7 0x03 6 0x03 5:4 0x03 3:0 0x04 7:4 0x04 3:1 0x04 0 0x05 7:4 0x05 3:1 0x05 0 0x06 7:4 0x06 3:0 0x07 7 0x07 6 0x07 5 0x07 4:0 ...
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Register Register Name Address Bits PLL Control 0x08 7:2 0x08 1:0 0x09 7 0x09 6:5 0x09 4:3 0x09 2:0 Misc. Control 0x0A 7:5 0x0A 4:0 I DAC Control 0x0C 1:0 0x0B 7:0 0x0C 7 0x0C 6 AUX DAC1 Control 0x0E ...
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AD9776A/AD9778A/AD9779A Register Register Name Address Bits AUX DAC2 Control 0x12 1:0 0x11 7:0 0x12 7 0x12 6 0x12 5 Interrupt 0x19 7 0x19 6 0x19 4 0x19 3 0x19 2 0x19 0 Version 0x1F 7:0 Parameter Function Auxiliary DAC2 Data<9:8> ...
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INTERPOLATION FILTER ARCHITECTURE The AD9776A/AD9778A/AD9779A can provide up to 8× inter- polation, or the interpolation filters can be entirely disabled important to note that the input signal should be backed off by approximately 0.01 dB from full scale ...
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AD9776A/AD9778A/AD9779A 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 – (× Input Data Rate) OUT Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB ...
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Input Data Rate) OUT Figure 64. Interpolation/Modulation Combination of − –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD9776A/AD9778A/AD9779A Table 19. Interpolation Filter Modes, (Register 0x01, Bits<5:2>) Interpolation Factor<7:6> Filter Mode<5:2> 8 0x00 8 0x01 8 0x02 8 0x03 8 0x04 8 0x05 8 0x06 8 0x07 8 0x08 8 0x09 8 0x0A 8 0x0B 8 0x0C 8 ...
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INTERPOLATION FILTER BANDWIDTH LIMITS The AD9776A/AD9778A/AD9779A use a novel interpolation filter architecture that allows DAC IF frequencies to be gener- ated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note that there ...
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AD9776A/AD9778A/AD9779A SOURCING THE DAC SAMPLE CLOCK The AD9776A/AD9778A/AD9779A offer two modes of sourcing the DAC sample clock (DACCLK). The first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the ...
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Table 21. Typical VCO Frequency Range vs. PLL Band Select Value PLL Lock Ranges over Temperature, −40°C to +85°C VCO Frequency Range in MHz PLL Band Select f LOW 111111 (63) Auto mode 111110 (62) 1975 111101 (61) 1956 111100 ...
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AD9776A/AD9778A/AD9779A If the optimal band is in the range (higher VCO frequency), refer to Table 23. Table 23. Setting Optimal PLL Band, When Band Is in the Higher Range (32 to 62) If System Startup Temperature ...
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FULL-SCALE CURRENT GENERATION INTERNAL REFERENCE Full-scale current on the I DAC and Q DAC can be set from 8. 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external ...
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AD9776A/AD9778A/AD9779A TRANSMIT PATH GAIN AND OFFSET CORRECTION Analog quadrature modulators make it very easy to realize single sideband radios. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are • Gain mismatch—the gain in the ...
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QUADRATURE MODULATOR V+ AD9779A 0.1µF OPTIONAL AD9779A QUAD MOD PASSIVE I DAC I INPUTS FILTERING 0.1µF 25Ω TO 50Ω 0.1µF OPTIONAL AD9779A PASSIVE Q DAC FILTERING 0.1µF 25Ω TO 50Ω Figure 78. Typical Use of Auxiliary DACs AC Coupling to ...
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AD9776A/AD9778A/AD9779A INPUT DATA PORTS The AD9776A/AD9778A/AD9779A can operate in two data input modes: dual port mode and single port mode. For the default dual port mode (Single Port = 0), each DAC receives data from a dedicated input port. In ...
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The DATACLKDIV only affects the DATACLK output frequency and not the frequency of the data sampling clock. To maintain an f frequency that samples the input data that remains DATACLK consistent with the expected data rate, DATACLKDIV should be set ...
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AD9776A/AD9778A/AD9779A OPTIMIZING THE DATA INPUT TIMING The AD9776A/AD9778A/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP, the internal clock that samples the input data. This ...
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DEVICE SYNCHRONIZATION System demands can impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other. This is the case when supporting transmit diversity or beam forming, where multiple antennas are used to transmit ...
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AD9776A/AD9778A/AD9779A SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9776A/AD9778A/AD9779A offer a pulse mode synchro- nization scheme (see Figure 89) to align the DAC outputs of multiple devices within a system to the same DAC clock edge. The internal clocks are ...
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POWER DISSIPATION Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC and dual DAC modes. In addition to this, the power dissipation/current of the 3.3 V ...
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AD9776A/AD9778A/AD9779A 0.125 8× INTERPOLATION, f /8, DAC f /4, DAC f /2, DAC NO MODULATION 0.100 4× INTERPOLATION 0.075 0.050 0.025 100 125 150 f (MSPS) DATA Figure 97. Power Dissipation, Clock 1.8 V Supply, ...
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EVALUATION BOARD OPERATION The AD9776A/AD9778A/AD9779A evaluation board is designed to optimize the DAC performance and the speed of the digital interface, yet remains user friendly. To operate the board, the user needs a power source, a clock source, and a ...
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AD9776A/AD9778A/AD9779A The evaluation board comes with software that allows the user to program the SPI port. Via the SPI port, the devices can be programmed into any of its various operating modes. When first operating the evaluation board ...
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USING THE ADL5372 QUADRATURE MODULATOR The evaluation board contains an Analog Devices ADL5372 quadrature modulator. The AD9776A/AD9778A/AD9779A and ADL5372 provide an easy-to-interface DAC/modulator combination that can be easily characterized on the evaluation board. Solderable jumpers can be configured to evaluate ...
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AD9776A/AD9778A/AD9779A EVALUATION BOARD SCHEMATICS Figure 105. Evaluation Board, Rev. A, Power Supply and Decoupling Rev Page 06452-203 RC0805 RC0805 ...
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R22 2 DNP R21 10K R63 GND SW1 RED TP12 TP11 RED ...
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AD9776A/AD9778A/AD9779A DNP 0603 RC R24 Figure 107. Evaluation Board, Rev. A, ADL5372 (FMOD2) Quadrature Modulator DNP 21 0603 RC 22 R23 23 24 PAD Rev Page 06452-205 100PF ...
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RC0402 RC0402 RC0402 RC0402 CC0402 CC0402 RC0402 Figure 108. Evaluation Board, Rev DAC Clock Interface Rev Page AD9776A/AD9778A/AD9779A 06452-206 ...
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AD9776A/AD9778A/AD9779A Figure 109. Evaluation Board, Rev. A, Digital Input Data Lines Rev Page 06452-207 ...
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Figure 110. Evaluation Board, Rev. A, On-Board Power Supply Rev Page AD9776A/AD9778A/AD9779A 06452-208 ...
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AD9776A/AD9778A/AD9779A Figure 111. Evaluation Board, Rev A, Top Side Silk Screen Rev Page ...
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Figure 112. Evaluation Board, Rev. A, Bottom Side Silk Screen Rev Page AD9776A/AD9778A/AD9779A ...
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... AD9778ABSVZ −40°C to +85°C 1 AD9778ABSVZRL −40°C to +85°C 1 AD9779ABSVZ −40°C to +85°C 1 AD9779ABSVZRL −40°C to +85°C 1 AD9776A-EBZ 1 AD9778A-EBZ 1 AD9779A-EBZ RoHS Compliant Part. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...