CAT5261YI-00 ON Semiconductor, CAT5261YI-00 Datasheet - Page 7

• Manufacturer Part Number: CAT5261YI-00
• Manufacturer: ON Semiconductor

Specifications of CAT5261YI-00

• Number Of Elements: 2
• # Of Taps: 256
• Resistance (max): 100KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (SPI)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: TSSOP
• Lead Free Status / Rohs Status: Compliant

Figure 2. HOLD
INSTRUCTION AND REGISTER
DESCRIPTION
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5261 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5261 are fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the CAT5261 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
HOLD
SCK
SO
CS
¯¯¯¯¯ Timing
(MSB)
(MSB)
ID3
I3
0
ID2
I2
1
Device Type
Identifier
Instruction
Opcode
t HD
t CD
ID1
I1
0
t HZ
ID0
I0
1
7
by CMOS input signals or tied to V
remaining two bits in the device address byte must be
set to 0.
INSTRUCTION BYTE
The next byte sent to the CAT5261 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I3 - I0. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
Data Register Selection
Data Register Selected
R1
A3
HIGH IMPEDANCE
Data Register
t HD
Selection
DR0
DR1
R0
A2
Slave Address
t CD
t LZ
WCR/Pot Selection
A1
P1
R1
0
0
(LSB)
(LSB)
A0
P0
R0
0
1
CC
Doc. No. MD-2122 Rev. G
or V
CAT5261
SS
. The