MAX5259EEE+T Maxim Integrated Products, MAX5259EEE+T Datasheet - Page 14

• Manufacturer Part Number: MAX5259EEE+T
• Description: IC DAC 8BIT OCTAL 3V 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5259EEE+T

• Settling Time: 10µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

All eight DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog
value within the reference range. This command can be used to substitute CLEAR if code 00 (hex) is programmed,
which clears all DACs. This command brings the device out of shutdown.
When performing a single update operation, A2-A0 selects the respective input register. At the rising edge of CS, the
selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This pre-
loads individual data in the input register without changing the DAC outputs.
This command directly loads current shift-register data in the selected input and DAC registers at the rising edge of
CS. A2-A0 set the DAC address.
For example, to load all eight DAC registers simultaneously with individual settings, eight commands are required.
First perform seven single input register update operations (C2 = 1, C1 = 0, C0 = 1) for DACs A, B, C, D, E, F, and G
(C2 = 1, C1 = 0, C0 = 1). The final command loads input register H and updates all eight DAC registers from their
respective input registers. This command brings the device out of shutdown.
All DAC registers are updated with the contents of their respective input registers at the rising edge of CS. This is a
synchronous software command that performs the same function as the asynchronous LDAC.
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
(LDAC = X)
(LDAC = X)
(LDAC = X)
(LDAC = X)
14
A2
A2
A2
A2
______________________________________________________________________________________
Don’t Care
Address
Address
Address
A1
A1
A1
A1
A0
A0
A0
A0
C2
C2
C2
C2
1
1
1
1
C1
C1
C1
C1
Load Input Register, DAC Registers Unchanged (Single Update Operation)
0
1
1
0
C0
C0
C0
C0
1
0
0
1
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
Load All DACs with Shift-Register Data
D4
D4
D4
D4
8-Bit Data
8-Bit Data
8-Bit Data
8-Bit Data
Load Input and DAC Registers
Software “
D3
D3
D3
D3
D2
D2
D2
D2
LDAC ” Command
D1
D1
D1
D1
D0
D0
D0
D0