74LVT574PW NXP Semiconductors, 74LVT574PW Datasheet - Page 3

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74LVT574PW

Manufacturer Part Number
74LVT574PW
Description
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin TSSOP Tube
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVT574PW

Package
20TSSOP
Logic Function
D-Type Bus Interface
Logic Family
LVT
Number Of Element Outputs
8
Output Signal Type
Single-Ended
Output Type
3-State
Number Of Output Enables Per Element
1
Typical Operating Supply Voltage
3.3 V
Operating Temperature
-40 to 85 °C

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NXP Semiconductors
5. Pinning information
Table 2.
74LVT_LVTH574_4
Product data sheet
Symbol
OE
D0 to D7
GND
CP
Q0 to Q7
V
Fig 4.
CC
Pin configuration for SO20, and (T)SSOP20
Pin description
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
5.1 Pinning
5.2 Pin description
10
1
2
3
4
5
6
7
8
9
74LVTH574
74LVT574
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
001aae758
20
19
18
17
16
15
14
13
12
11
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
CC
Rev. 04 — 11 September 2008
Fig 5.
(1) The die substrate is attached to this pad using
Description
output enable input (active LOW)
data input
ground (0 V)
clock pulse input (active rising edge)
data output
supply voltage
74LVT574; 74LVTH574
conductive die attach material. It can not be used as a
supply pin or input
Pin configuration for DHVQFN20
index area
terminal 1
D0
D1
D2
D3
D4
D5
D6
D7
3.3 V octal D-type flip-flop; 3-state
Transparent top view
2
3
4
5
6
7
8
9
74LVTH574
74LVT574
GND
(1)
19
18
17
16
15
14
13
12
001aah711
© NXP B.V. 2008. All rights reserved.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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