ISPLSI 2064E-100LT100 Lattice, ISPLSI 2064E-100LT100 Datasheet
ISPLSI 2064E-100LT100
Specifications of ISPLSI 2064E-100LT100
Related parts for ISPLSI 2064E-100LT100
ISPLSI 2064E-100LT100 Summary of contents
Page 1
... The basic unit of logic on the ispLSI 2064E device is the Generic Logic Block (GLB). The GLBs are labeled A0 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064E device. Each GLB is made up of four macrocells ...
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... Input Bus GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2 asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock ...
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... Input High Voltage IH Capacitance (TA=25°C, f=1.0 MHz) SYMBOL PARAMETER C Dedicated Input Capacitance 1 C I/O Capacitance 2 C Clock Capacitance 3 Erase/Reprogram Specification PARAMETER Erase/Reprogram Cycles Specifications ispLSI 2064E 1 -0.5 to +7.0V +1.0V CC +1.0V CC PARAMETER T = 0°C to +70° 3.3V TYPICAL MINIMUM 10,000 3 MIN. ...
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... Maximum I varies widely with specific device configuration and operating frequency. Refer to the CC Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I Specifications ispLSI 2064E Figure 2. Test Load GND to 3.0V 1.5 ns 1.5V 1 ...
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... Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 2064E Over Recommended Operating Conditions 1 DESCRIPTION ...
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... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2064E 1 Over Recommended Operating Conditions DESCRIPTION 3 ...
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... Clock (max) + Reg co + Output grp + ptck(max (#20 + #22 + #35) + (#31) + (#36 + #38) 7.9ns = (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6) Note: Calculations are based upon timing specifications for the ispLSI 2064E-200L. Specifications ispLSI 2064E GRP GLB Feedback Comb 4 PT Bypass #23 GRP Reg 4 PT Bypass #22 # XOR Delays #25, 26, 27 Control ...
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... I CC can be estimated for the ispLSI 2064E using the following equation (mA PTs * 0.75 nets * Max freq * 0.004) Where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I CC estimate is based on typical conditions ( 5.0V, room temperature) and an assumption of two GLB loads on average exists ...
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... VCCIO 1, 24 10, 26, 50, 61, 89, 99 pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. Specifications ispLSI 2064E 19, 20, Input/Output Pins - These are the general purpose I/O pins used by the 23, 28, logic array. 31, 32, 35, 36, 42, 43, ...
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... Pin Configuration ispLSI 2064E 100-Pin TQFP Pinout Diagram VCCIO 1 GND VCC 12 GND 13 BSCAN 14 RESET 15 2 TDI VCCIO 24 GND pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. Specifications ispLSI 2064E ...
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... Specifications ispLSI 2064E – XXX X XXXX COMMERCIAL ORDERING NUMBER 4.5 ispLSI 2064E-200LT100 7.5 ispLSI 2064E-135LT100 ispLSI 2064E-100LT100 Grade Blank = Commercial Package T100 = TQFP Power L = Low 0212/2064E PACKAGE 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Table 2-0041A/2064E ...