MAX534AEEE Maxim Integrated Products, MAX534AEEE Datasheet - Page 11

• Manufacturer Part Number: MAX534AEEE
• Description: IC DAC QUAD +5V 8BIT R/R 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX534AEEE

• Settling Time: 8µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 667mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The MAX534 is Microwire™ and SPI™/QSPI™ compati-
ble (Figures 4 and 5). For SPI and QSPI, clear the
CPOL and CPHA configuration bits (CPOL = CPHA =
0). The SPI/QSPI CPOL = CPHA = 1 configuration can
also be used if the DOUT output is ignored.
The MAX534 can interface with Intel’s 80C5X/80C3X
family in mode 0 if the SCLK clock polarity is inverted.
More universally, if a serial port is not available, three
lines from one of the parallel ports can be used for bit
manipulation.
Digital feedthrough at the voltage outputs is greatly
minimized by operating the serial clock only to update
the registers. The clock idle state is low.
Any number of MAX534s can be daisy-chained by con-
necting DOUT of one device to DIN of the following
device in the chain. The NOP instruction (Table 1)
allows data to be passed from DIN to DOUT without
changing the input or DAC registers of the passing
device. A 3-wire interface updates daisy-chained or
individual MAX534s simultaneously by bringing CS
high (Figure 6).
Figure 6. Daisy-chained or individual MAX534s are simultaneously updated by bringing CS high. Only three wires are required.
SCLK
SCLK
DIN
DIN
CS
CS
______________________________________________________________________________________
Interfacing to the Microprocessor
SCLK
DIN
CS
SCLK
DIN
CS
DEVICE A
MAX534
MAX534
Daisy-Chaining Devices
DOUT
+5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
SCLK
DIN
CS
MAX534
DEVICE B
The MAX534 uses a matrix decoding architecture for
the DACs, which saves power in the overall system.
The external reference voltage is divided down by a
resistor string placed in a matrix fashion. Row and col-
umn decoders select the appropriate tab from the
resistor string to provide the needed analog voltages.
The resistor string presents a code-independent input
impedance to the reference and guarantees a mono-
tonic output. Figure 8 shows a simplified diagram of the
four DACs.
The voltage at REF sets the full-scale output voltage for
all four DACs. The 460kΩ typical input impedance at
REF is code independent. The output voltage for any
DAC can be represented by a digitally programmable
voltage source as follows:
where NB is the numerical value of the DAC’s binary
input code.
DOUT
V
OUT
= (NB x V
SCLK
DIN
CS
MAX534
DEVICE C
REF
DOUT
) / 256
Analog Section
Reference Input
DAC Operation
TO OTHER
SERIAL DEVICES
11