LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 23

• Manufacturer Part Number: LC5512MB-75F256I
• Description: LATLC5512MB-75F256I 512MC CPLD 150K Gate
• Manufacturer: Lattice

Lattice Semiconductor
DC Electrical Characteristics
I
I
I
I
I
I
I
I
V
C1
C2
C3
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured
2. T
3. I
4. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ V
IL,
IH
PU
PD
BHLS
BHHS
BHLO
BHHO
Symbol
BHT
4
with the output driver active. Bus maintenance circuits are disabled.
5V tolerant interface.
3
I
PU
A
IH
25°C, f=1.0MHz
1
on JTAG pins has a maximum of -175µA for 5512MX devices.
Input or I/O Leakage
Input High Leakage Current
I/O Active Pullup Current
I/O Active Pulldown Current
Bus Hold Low Sustaining Current V
Bus Hold High Sustaining Current V
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
I/O Capacitance
Clock Capacitance
Global Input Capacitance
Parameter
2
2
2
Over Recommended Operating Conditions
0 ≤ V
(V
3.6V < V
3.0V ≤ V
0 ≤ V
V
0 ≤ V
0 ≤ V
0 ≤ V
V
V
V
V
V
V
IL
IN
IN
CCO
CC
CCO
CC
CCO
CC
CCO
(MAX) ≤ V
= V
= 0.7 V
= 1.8V, V
= 1.8V, V
= 1.8V, V
IN
IN
IN
IN
IN
= 3.3V, 2.5V, 1.8V
= 3.3V, 2.5V, 1.8V
= 3.3V, 2.5V, 1.8V
- 0.2V) < V
IL
≤ (V
≤ 0.7 V
≤ V
≤ V
≤ V
IN
CCO
(MAX)
IH
IH
IH
≤ 5.5V and
CCO
Condition
CCO
≤ 3.6V
(MAX)
(MAX)
(MAX)
IO
IO
IO
IN
CCO
23
- 0.2V)
= 0 to V
= 0 to V
= 0 to V
≤ V
IN
CCO
IH
≤ 3.6V
(MAX)
≤ 3.6V. The JTAG and sysCONFIG ports are not included for the
IH
IH
IH
(MAX)
(MAX)
(MAX)
ispXPLD 5000MX Family Data Sheet
V
CCO
Min.
-30
30
30
30
—
—
—
—
—
—
—
—
—
—
—
* 0.35
Typ.
—
—
—
—
—
—
—
—
—
—
8
8
8
8
8
8
V
CCO
Max.
-150
150
150
150
10
40
—
—
—
—
—
—
—
—
3
* 0.65
Units
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
pf
pf
pf
pf
pf
pf