A3950SEUTR-T Allegro, A3950SEUTR-T Datasheet

A3950SEUTR-T

Manufacturer Part Number

A3950SEUTR-T

Description

Manufacturer

Allegro

Datasheets

1.A3950SEUTR-T.pdf (12 pages)

2.A3950SEUTR-T.pdf (12 pages)

3.A3950SEUTR-T.pdf (12 pages)

4.A3950SLPTR-T.pdf (12 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

A3950SEUTR-T

Manufacturer:

ALLEGRO/雅丽高

Quantity:

20 000

Company:

H&T Electronics

Part Number:

A3950SEUTR-T

Quantity:

6 000

Current page: 1 of 12
Download datasheet (524Kb)

Package LP, 16 pin TSSOP

with Exposed Thermal Pad

Features and Benefits

▪ Low R

▪ Overcurrent protection

▪ Motor lead short-to-supply protection

▪ Short-to-ground protection

▪ Sleep function

▪ Synchronous rectification

▪ Diagnostic output

▪ Internal undervoltage lockout (UVLO)

▪ Crossover-current protection

Packages:

A3950DS, Rev. 5

5 kΩ

DS(on)

PHASE

GND

SLEEP

ENABLE

outputs

Approximate Scale 1:1

EU Package

Package EU

A3950

with Exposed Thermal Pad

Package EU, 16 pin QFN

OUTB

0.22 μF

25 V

0.1 μF

50 V

GND

CP2

CP1

Typical Application Diagrams

0.1 μF

50 V

0.1 μF

50 V

100 μF

50 V

DMOS Full-Bridge Motor Driver

Description

Designed for PWM (pulse width modulated) control of DC

motors, the A3950 is capable of peak output currents to ±2.8 A

and operating voltages to 36 V.

PHASE and ENABLE input terminals are provided for use in

controlling the speed and direction of a DC motor with externally

applied PWM control signals. Internal synchronous rectification

control circuitry is provided to lower power dissipation during

PWM operation.

Internal circuit protection includes motor lead short-to-

supply / short-to-ground, thermal shutdown with hysteresis,

undervoltage monitoring of V

protection.

The A3950 is supplied in a thin profile (<1.2 mm overall height)

16 pin TSSOP package (LP), and a very thin (0.75 mm nominal

height) QFN package. Both packages provide an exposed pad

for enhanced thermal dissipation, and are lead (Pb) free with

100% matte tin leadframe plating.

5 kΩ

MODE

PHASE

GND

SLEEP

ENABLE

OUTA

SENSE

NFAULT

LP Package

Package LP

A3950

and V

VREG

OUTB

GND

VCP

VBB

CP2

CP1

0.1 μF

50 V

, and crossover-current

0.1 μF

50 V

0.1 μF

50 V

A3950

0.22 μF

25 V

100 μF

50 V

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