SI5338M-A-GMR Silicon Laboratories Inc, SI5338M-A-GMR Datasheet - Page 22

• Manufacturer Part Number: SI5338M-A-GMR
• Manufacturer: Silicon Laboratories Inc

Si5338
3.5.4. Modifying a MultiSynth Output Divider Ratio/
The output MultiSynth dividers of a configured and
phase-locked Si5338 can be modified without relocking
the PLL (i.e. without following section 3.5.3). This
feature allows any of the four output frequencies to be
modified without disturbing the others.
In this case, only write the set of registers associated
with
Frequency Configuration; see Section 6.2). The
feedback MultiSynth must not be modified unless
following the procedure in Section 3.5.3.
To avoid intermediate frequencies, it is recommended
that the output be disabled before changing the divider
ratio (see Register 230).
Any output MultiSynth that is reconfigured will lose its
phase alignment with the other outputs. SOFT_RESET
can be used to resynchronize the outputs (see "3.8.
Reset Options" on page 23).
3.5.5. Writing a Custom Configuration to NVM
An alternative to ordering an Si5338 with a custom NVM
configuration is to use the field programming kit
(Si5338-PROG-EVB) to write directly to the NVM of a
"blank" Si5338. Since NVM is an OTP memory, it can
only be written once. The default configuration can be
reconfigured by writing to RAM through the I
(see “3.5.2. Creating a New Configuration for RAM”).
3.6. Status Indicators
A logic-high interrupt pin (INTR) is available to indicate
a loss of signal (LOS) condition, a PLL loss of lock
(PLL_LOL) condition, or that the PLL is in process of
acquiring lock (SYS_CAL). PLL_LOL is held high when
the input frequency drifts beyond the PLL lock range. It
is held low during all other times and during a POR or
soft reset. SYS_CAL is held high during a POR or SOFT
reset so that no chattering occurs during the locking
process. As shown in Figure 10, a status register at
address 218 is available to help identify the exact event
that caused the interrupt pin to become active.
Figure 11 shows a typical connection with the required
pull-up resistor to VDD.
22
218
Frequency Configuration
the
7
6
Figure 10. Status Register
output
5
PLL_LOL
4
MultiSynth
LOS_FDBK LOS_CLKIN
3
2
divider
1
Sys
Cal
0
2
System Calibration
(Lock Acquisition)
Loss Of Signal
Clock Input
Loss Of Lock
Loss Of Signal
Feedback Input
(MultiSynth
C interface
Rev. 0.6
3.6.1. Using the INTR Pin in Systems with I
The INTR output pin is not latched and thus it should not
be a polled input to an MCU but an edge-triggered
interrupt. An MCU can process an interrupt event by
reading the sticky register 247 to see what event
caused the interrupt. The same register can be cleared
by writing zeros to the bits that were set. Individual
interrupt bits can be masked by register 6[4:0].
3.6.2. Using the INTR Pin in Systems without I
The INTR pin also provides a useful function in systems
that require a pin-controlled fault indicator. Pre-setting
the interrupt mask register allows the INTR pin to
become an indicator for a specific event, such as LOS
and/or LOL. Therefore, the INTR pin can be used to
indicate a single fault event or even multiple events.
3.7. Output Enable
There are two methods of enabling and disabling the
output drivers: Pin control, and I
3.7.1. Enabling Outputs Using Pin Control
The Si5338K/L/M devices provide an Output Enable pin
(OEB) as shown in Figure 12. Pulling this pin high will
turn all outputs off. The state of the individual drivers
when turned off is controllable. If an individual output is
set to always on, then the OEB pin will not have an
effect on that driver. Drive state options and always on
are explained in “3.7.2. Enabling Outputs through the
I
2
C Interface”.
Figure 12. Output Enable Pin (Si5338K/L/M)
1 = Disabled
Figure 11. INTR Pin with Required Pull-Up
0 = Enabled
1k
V
DD
INTR
OEB
Control
Control & Memory
Control
Control & Memory
2
(OTP)
C control.
NVM
(OTP)
NVM
RAM
RAM
2
C
2
C