MAX5856AECM+D Maxim Integrated Products, MAX5856AECM+D Datasheet - Page 5

• Manufacturer Part Number: MAX5856AECM+D
• Description: IC DAC 8BIT DUAL 300MSPS 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5856AECM+D

• Settling Time: 11ns
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 792mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(AV
V
guaranteed by production test. T
Clock Frequency at CLK Input
Output Settling Time
Output Rise Time
Output Fall Time
Data-to-CLK Rise Setup Time
(Note 3)
Data-to-CLK Rise Hold Time
(Note 3)
Data-to-CLK Fall Setup Time
(Note 3)
Data-to-CLK Fall Hold Time
(Note 3)
Control Word to CW Fall Setup
Time
Control Word to CW Fall Hold
Time
CW High Time
CW Low Time
DACEN Rise-to-V
PD Fall-to-V
Clock Frequency at
CLKXP/CLKXN Input
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
Minimum CLKXP/CLKXN Clock
High Time
Minimum CLKXP/CLKXN Clock
Low Time
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
REFO
DD
= 1.2V, I
= DV
PARAMETER
DD
OUT
FS
= PV
Stable
OUT
= 20mA, output amplitude = 0dB FS, differential output, T
_______________________________________________________________________________________
DD
Stable
= 3V, AGND = DGND = PGND = 0, f
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
A
< +25°C, guaranteed by design and characterization. Typical values are at T
SYMBOL
f
CLKDIFF
t
t
t
t
I
DV
t
PDSTB
AV
t
DCHR
t
f
DCSR
DCHF
t
t
AVDD
DCSF
t
t
CWS
CWH
CLK
CXD
CXH
STB
CXL
t
s
DD
DD
No interpolation, PLL enabled
2x interpolation, PLL enabled
4x interpolation, PLL enabled
To ±0.1% error band (Note 2)
10% to 90% (Note 2)
90% to 10% (Note 2)
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
External reference
Differential clock, PLL disabled
PLL disabled
(Note 4)
Interpolation Filters and PLL
DAC
CONDITIONS
= 165Msps, no interpolation, PLL disabled, external reference,
A
= T
MIN
to T
MAX
, unless otherwise noted. T
37.5
MIN
1.5
2.2
0.4
1.4
1.8
2.4
1.2
1.3
2.5
2.5
2.7
2.7
75
5
5
TYP
2.5
2.5
0.7
0.5
4.6
1.5
1.5
11
44
A
= +25°C.)
MAX
165
150
300
3.3
3.3
75
47
A
> +25°C,
UNITS
MHz
MHz
mA
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
V
V
5