A3PN030-ZQNG68I Actel, A3PN030-ZQNG68I Datasheet - Page 65

• Manufacturer Part Number: A3PN030-ZQNG68I
• Manufacturer: Actel

Clock Conditioning Circuits
Table 2-69 • ProASIC3 nano CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable
Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific
4. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
junction temperature and voltage supply levels, refer to
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
J
= 25°C, V
CCC Electrical Specifications
Timing Characteristics
5
CC
= 1.5 V
1,2
3
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
CCC_OUT
1,2
1,2
IN_CCC
OUT_CCC
1,2
A dv a n c e v 0. 2
Minimum
Table 2-6 on page 2-5
Table 2-6 on page 2-5
Network
1 Global
0.50%
1.00%
1.75%
2.50%
0.025
Used
0.75
48.5
1.25
1.5
ProASIC3 nano DC and Switching Characteristics
Max Peak-to-Peak Period Jitter
External
FB Used
Typical
200
2.2
for deratings.
for derating values.
Maximum
Networks
3 Global
0.70%
1.20%
2.00%
5.60%
15.65
15.65
Used
51.5
350
350
125
300
1.5
6.0
1.6
0.8
32
Units
MHz
MHz
MHz
ms
ps
ns
µs
ns
ns
%
ns
ns
ns
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