EMC2103-2-AP-TR Standard Microsystems (SMSC), EMC2103-2-AP-TR Datasheet - Page 67

• Manufacturer Part Number: EMC2103-2-AP-TR
• Description: CLOSED LOOP RPM FAN CONTROLLER
• Manufacturer: Standard Microsystems (SMSC)

RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
SMSC EMC2103
6.37
6.38
ADDR
ADDR
E5h
E4h
R/W
R/W
R/W
R/W
The GPIO Input Register indicates the state of the corresponding GPIO pin. When a GPIO is
configured as an input, any change of state will assert the ALERT# pin (unless GPIO interrupts are
masked, see
Bit 1 - GPIO2_IN - Indicates the pin state of the GPIO2 pin regardless of the pin functionality.
Bit 0 - GPIO1_IN - Indicates the pin state of the GPIO1 pin regardless of the pin functionality.
The GPIO Output Register controls the state of the corresponding pins when they are configured as
outputs.
If the output is configured as an open-drain output, then it requires a pull-up resistor to VDD. Setting
the corresponding bit to a ‘1’ will act to disable the output allowing the pull-up resistor to pull the output
high. Setting the corresponding bit to a ‘0’ will enable the output and drive the pin to a logical ‘0’ state.
If the output is configured as a push-pull output, then output pin will immediately be driven to match
the corresponding bit setting.
Bit 1 - GPIO2_OUT - Controls the pin state of the GPIO2 pin when it is configured as a GPIO output.
Bit 0 - GPIO1_OUT - Controls the pin state of the GPIO1 pin when it is configured as a GPIO output.
The GPIO Interrupt Enable Register enables the GPIOs to assert the ALERT pin when they change
state. When the GPIO pins are configured as outputs, then these bits are ignored.
Bit 1 - GPIO2_INT_EN - Allows the ALERT pin to be asserted when the GPIO2 pin changes state
(when configured as an input).
Bit 0 - GPIO1_INT_EN - Allows the ALERT pin to be asserted when the GPIO1 pin changes state
(when configured as an input).
GPIO Output Register (EMC2103-2 Only)
GPIO Interrupt Enable Register (EMC2103-2 Only)
‘0’ (default) - The ALERT pin will not be asserted when the GPIO2 pin changes state (when
configured as an input).
‘1’ - The ALERT pin will be asserted when the GPIO2 pin changes state (when configured as an
input)
‘0’ (default) - The ALERT pin will not be asserted when the GPIO1 pin changes state (when
configured as an input).
REGISTER
Interrupt
REGISTER
Enable
GPIO
Output 1
GPIO
Section
Table 6.55 GPIO Interrupt Enable Register
6.15).
B7
-
B7
-
Table 6.54 GPIO Output Register
B6
-
B6
-
DATASHEET
B5
B5
67
B4
B4
B3
B3
B2
B2
GPIO2_
INT_EN
GPIO2
B1
_OUT
B1
GPIO1_
INT_EN
GPIO1
Revision 0.88 (06-30-08)
_OUT
B0
B0
DEFAULT
DEFAULT
00h
00h