AD9751AST Analog Devices Inc, AD9751AST Datasheet
AD9751AST
Specifications of AD9751AST
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AD9751AST Summary of contents
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FEATURES 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single ...
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AD9751–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range ...
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DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f DAC Output Settling Time (t ) (to 0.1 Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time ...
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AD9751 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Logic 0 Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time ( 25° Input Hold Time ( 25° Latch Pulsewidth ...
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... With Respect to ACOM, DCOM, CLKCOM, PLLCOM AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM ACOM ACOM DCOM CLKCOM CLKCOM PLLCOM Model AD9751AST AD9751ASTRL –40°C to +85°C 48-Lead LQFP ST-48 AD9751- DATA Y DATA X THERMAL CHARACTERISTIC Thermal Resistance θ 91°C/W JA –5– ...
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AD9751 MSB–P1B9 Pin No. Mnemonic 1 RESET 2 CLK+ 3 CLK– DCOM 5, 21 DVDD 6 PLLLOCK 7–16 P1B9–P1B0 17–20, 33–36 RESERVED 23–32 P2B9–P2B0 37, 38 DIV0, DIV1 39 REFIO 40 FSADJ 41 AVDD 42 I OUTB 43 ...
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TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) ...
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AD9751–Typical Performance Characteristics 90 0dBFS 80 70 –6dBFS –12dBFS (MHz) OUT TPC 1. Single-Tone SFDR vs OUT MSPS; Single Port Mode DAC 90 ...
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A (dBm) OUT TPC 10. Two-Tone IMD (to Nyquist) vs ...
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AD9751 FUNCTIONAL DESCRIPTION Figure 3 shows a simplified block diagram of the AD9751. The AD9751 consists of a PMOS current source array capable of providing full-scale current, I divided into 31 equal sources that make ...
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OPTIONAL EXTERNAL REFERENCE BUFFER 1.2V REF REFIO ADDITIONAL 0.1 F FSADJ EXTERNAL LOAD I 2k REF Figure 4. Internal Reference Configuration AD9751 REFERENCE SECTION AVDD 1.2V REF REFIO EXTERNAL REFERENCE FSADJ I 2k REF Figure 5. External Reference Configuration PLL ...
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AD9751 The effects of phase noise on the AD9751’s SNR performance become more noticeable at higher reconstructed output fre- quencies and signal levels. Figure 8 compares the phase noise of a full-scale sine wave at exactly different ...
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INTERLEAVED (2 ) MODE WITH PLL DISABLED The relationship between the internal and external clocks in this mode is shown in Figure 11. A clock at the output update data rate (2× the input data rate) must be applied to ...
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AD9751 Equations 7 and 8 highlight some of the advantages of operating the AD9751 differentially. First, the differential operation helps cancel common-mode error sources associated with I I such as noise, distortion, and dc offsets. Second, the OUTB differential code-dependent ...
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CLK–, can be driven from a single-ended or differential clock source. For single-ended operation, CLK+ should be driven by a logic source while CLK– should be set to the threshold voltage of the logic source. This can be done via ...
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AD9751 2.5 5 7.5 10 12.5 I (mA) OUTFS Figure 17. I vs. I AVDD 300MSPS 12 10 200MSPS 8 100MSPS 6 50MSPS 4 25MSPS 2 ...
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The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both I and I . The complementary voltages appearing OUTA OUTB at I and I (i.e., V ...
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AD9751 C OPT R FB 200 AD9751 I OUTA I OUTB 200 Figure 24. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In ...
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APPLICATIONS QAM/PSK Synthesis Quadrature modulation (QAM or PSK) consists of two baseband PAM (Pulse Amplitude Modulated) data channels. Both chan- nels are modulated by a common frequency carrier. However, the carriers for each channel are phase-shifted 90° from each other. ...
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AD9751 CLK+ CLK– PLLLOCK PORT 1 INPUT DATA LATCHES INPUT PORT 2 INPUT DATA LATCHES INPUT FSADJ REFIO ACOM1 ACOM DCOM RSET2 1.9k 0.1 F Figure 30. QAM Transmitter Architecture Using AD9751 and AD8343 Active Mixer MARKER 1 [T2] RBW ...
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Pseudo Zero Stuffing/IF Mode The excellent dynamic range of the AD9751 allows its use in applications where synthesis of multiple carriers is desired. In addition, the AD9751 can be used in a pseudo zero stuffing mode, which improves dynamic range ...
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AD9751 RN2 VALUE RN1 1 VALUE 1B13 P1B13 1B12 P1B12 1B11 P1B11 1B10 P1B10 ...
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CLK+ 3 CLK– L1 DVDD FBEAD C13 10 F DGND 10V AVDD FBEAD J10 C14 10 F AGND 10V 1 J11 L3 CLKVDD FBEAD J12 C15 10 ...
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AD9751 Figure 36. Evaluation Board, Assembly—Top Figure 37. Evaluation Board, Assembly—Bottom –24– REV. C ...
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Figure 39. Evaluation Board, Layer 2, Ground Plane REV. C Figure 38. Evaluation Board, Top Layer –25– AD9751 ...
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AD9751 Figure 40. Evaluation Board, Layer 3, Power Plane Figure 41. Evaluation Board, Bottom Layer –26– REV. C ...
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SEATING 0.05 PLANE ROTATED 90 CCW REV. C OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 1 SEATING PLANE 10 6 0.20 2 0.09 VIEW ...
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AD9751 Revision History Location 9/03—Data Sheet changed from REV REV. C. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . ...