AD9777BSVRL Analog Devices Inc, AD9777BSVRL Datasheet
AD9777BSVRL
Specifications of AD9777BSVRL
Related parts for AD9777BSVRL
AD9777BSVRL Summary of contents
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FEATURES 16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment f / digital quadrature modulation capability S S Direct IF transmission mode for 70 MHz + IFs Enables image ...
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AD9777 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 4 Product Highlights ....................................................................... 4 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 Dynamic Specifications ............................................................... 6 Digital Specifications ................................................................... 7 Digital Filter Specifications ......................................................... 8 Absolute Maximum Ratings............................................................ 9 ...
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REVISION HISTORY 1/06—Rev Rev. C Updated Formatting .........................................................Universal Changes to Figure 32 .................................................................... 22 Changes to Figure 108 .................................................................. 54 Updated Outline Dimensions ..................................................... 58 Changes to Ordering Guide......................................................... 58 6/04—Data Sheet Changed from Rev Rev. ...
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AD9777 GENERAL DESCRIPTION 1 The AD9777 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC Accuracy Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT (for ...
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AD9777 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = MIN MAX transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE ...
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DIGITAL SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic ...
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AD9777 DIGITAL FILTER SPECIFICATIONS Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient − −134 ...
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ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, FSADJ1/FSADJ2 OUTA OUTB P1B15 to P1B0, P2B15 to P2B0, RESET DATACLK/PLL_LOCK CLK+, CLK− LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature Storage ...
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AD9777 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLKVDD LPF CLKVDD CLKGND CLK+ CLK– CLKGND DATACLK/PLL_LOCK DGND DVDD P1B15 (MSB) P1B14 P1B13 P1B12 P1B11 P1B10 DGND DVDD P1B9 P1B8 CONNECT ...
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Table 8. Pin Function Description Pin No. Mnemonic 1, 3 CLKVDD 2 LPF 4, 7 CLKGND 5 CLK+ 6 CLK− 8 DATACLK/PLL_LOCK 9, 17, 25, DGND 35, 44, 52 10, 18, 26, DVDD 36, 43 16, 19 ...
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AD9777 TERMINOLOGY Adjacent Channel Power Ratio (ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. ...
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TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Ω doubly terminated, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY ...
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AD9777 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 100 200 FREQUENCY (MHz) Figure 12. Single-Tone Spectrum @ f = 160 MSPS with f DATA 90 0dBFS –6dBFS –12dBFS ...
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FREQUENCY (MHz) Figure 18. Third-Order IMD Products vs. Two-Tone f Rate, 1× 160 MSPS, 2× f ...
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AD9777 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 FREQUENCY (MHz) Figure 24. Single-Tone Spurious Performance 150 MSPS, No Interpolation DATA 0 –20 –40 –60 –80 –100 ...
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FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance MSPS, Interpolation = 8× DATA 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD9777 MODE CONTROL (VIA SPI PORT) 1 Table 9. Mode Control via SPI Port Address Bit 7 Bit 6 00h SDIO LSB, MSB First Bidirectional 0 = MSB 0 = Input 1 = LSB 1 = I/O 01h Filter Filter ...
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Address Bit 7 Bit 6 0Ah 0Bh QDAC Offset QDAC Offset Adjustment Adjustment Bit 9 Bit 8 0Ch QDAC I OFFSET Direction OFFSET I OUTA OFFSET I OUTB 0Dh 1 Default values ...
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AD9777 REGISTER DESCRIPTION Address 00h Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or ...
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Address 03h Bit 7: This allows the data rate clock (divided down from the DAC clock output at either the DATACLK/PLL_LOCK pin (Pin the SPI_SDO pin (Pin 53). The default this register ...
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AD9777 FUNCTIONAL DESCRIPTION The AD9777 dual interpolating DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9777 ...
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INSTRUCTION BYTE The instruction byte contains the information shown below Description 0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes R/W Bit 7 of the instruction byte ...
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AD9777 INSTRUCTION CYCLE CS SCLK SDIO R (N) (N) SDO INSTRUCTION CYCLE CS SCLK SDIO SDO CS SCLK SDIO CS SCLK SDIO SDO ...
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NOTES ON SERIAL PORT OPERATION The AD9777 serial port configuration bits reside in Bit 6 and Bit 7 of Register Address 00h important to note that the configuration changes immediately upon writing to the last bit of the ...
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AD9777 0 –0.5 1R MODE –1.0 2R MODE –1.5 –2.0 –2.5 –3.0 0 200 400 600 FINE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9k Ω ) Figure 40. Fine Gain Effect Figure 42, the negative scale ...
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A configuration for differentially driving the clock inputs is given in Figure 44. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply ...
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AD9777 CLK+ CLK– PLL_LOCK 1 = LOCK LOCK INTERPOLATION PHASE FILTERS, DETECTOR MODULATORS, AND DACS CLOCK PRESCALER INPUT DISTRIBUTION DATA CIRCUITRY LATCHES INTERNAL SPI CONTROL REGISTERS INTERPOLATION RATE MODULATION CONTROL RATE SPI PORT ...
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POWER DISSIPATION The AD9777 has three voltage supplies: DVDD, AVDD, and CLKVDD. Figure 49, Figure 50, and Figure 51 show the current required from each of these supplies when each is set to the 3.3 V nominal specified for the ...
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AD9777 Register 3, Bit Register 1, Bit PLL lock indicator out of Pin 53. Register 3, Bit Register 1, Bit DATACLK out of Pin 8. Register 3, Bit ...
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The selection of the data for the channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, ...
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AD9777 t OD CLKIN DATACLK DATA AT PORTS 1 AND 6.5ns (MIN) TO 8.0ns (MAX 5.0ns (MAX –3.2ns (MAX) H Figure 55. Timing Requirements in Two-Port Input ...
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SINE DC –jωt e /2j –jωt –jω COSINE DC Figure 57. Real and Imaginary Components of Sinusoidal and Cosinusoidal Waveforms Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal ...
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AD9777 MODULATION, NO INTERPOLATION With Control Register 01h, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9777 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9777 in the ...
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MODULATION, INTERPOLATION = 2× With Control Register 01h, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9777 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, ...
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AD9777 MODULATION, INTERMODULATION = 4× With Control Register 01h, Bit 7 and Bit 6 set to 10, the interpolation rate of the AD9777 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence ...
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MODULATION, INTERMODULATION = 8× With Control Register 01h, Bits 7 and 6, set to 11, the interpolation rate of the AD9777 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, ...
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AD9777 ZERO STUFFING (Control Register 01h, Bit 3) As shown in Figure 75 null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f is ...
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INPUT (REAL) OUTPUT (REAL) INPUT (IMAGINARY) 90° OUTPUT (IMAGINARY) –jω COSωt + jSINωt Figure 77. Implementation of a Complex Modulator COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS In traditional transmit applications, a two-step upconversion is done in ...
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AD9777 REAL CHANNEL (IN IMAGINARY CHANNEL (IN REAL QUADRATURE MODULATOR IMAGINARY COMPLEX MODULATION FREQUENCY QUADRATURE MODULATION FREQUENCY Q REAL CHANNEL (OUT) A/2 1 –F C –B/2J –F C COMPLEX ...
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COMPLEX BASEBAND SIGNAL 1 e j(ω1 + ω2)t × OUTPUT = REAL 1/2 = REAL –ω1 – ω2 DC Figure 80. Two-Stage Complex Upconversion IMAGE REJECTION AND SIDEBAND SUPPRESSIONS OF MODULATED CARRIERS As shown in Figure 79, image rejection can ...
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AD9777 The complex carrier synthesized in the AD9777 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running result, complex modula- DAC tion ...
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–40 –60 –80 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 (LO (× ) OUT DATA Figure 83. 2× Interpolation, Complex f DAC 0 – ...
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AD9777 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (MHz) Figure 89. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9777 ...
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FREQUENCY (MHz) Figure 95. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8×, Complex Modulation in AD9777 = +f 0 –10 –20 –30 ...
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AD9777 APPLYING THE OUTPUT CONFIGURATIONS The following sections illustrate typical output configurations for the AD9777. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requiring OUTFS optimum dynamic performance, a differential output ...
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DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-single ended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9777 ...
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AD9777 EVALUATION BOARD The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Windows® 95, Windows 98, or Windows NT®/2000. The evaluation board also contains ...
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INPUT CLOCK AWG2021 OR DG2020 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – ...
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AD9777 INPUT CLOCK JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1 TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 ...
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RC0603 G2 ENBL G3 VPS1 VOUT LOIP VPS2 LOIN G4A G1B G4B G1A QBBN IBBN QBBP IBBP ADTL1-12 CC0603 Figure 105. AD8345 Circuitry on AD9777 Evaluation Board Rev Page RC0603 ADTL1-12 CC0805 AD9777 ...
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AD9777 CC0603 RC0603 CC0603 RC1206 CC0603 RC0603 CC0605 Figure 106. AD9777 Clock, Power Supplies, and Output Circuitry Rev Page CC0805 ...
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Figure 107. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev Page AD9777 ...
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AD9777 Figure 108. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev Page ...
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Figure 109. AD9777 Evaluation Board Components, Top Side Figure 110. AD9777 Evaluation Board Components, Bottom Side Rev Page AD9777 ...
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AD9777 Figure 112. AD9777 Evaluation Board Layout, Layer Two (Ground Plane) Figure 111. AD9777 Evaluation Board Layout, Layer One (Top) Rev Page ...
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Figure 113. AD9777 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9777 Evaluation Board Layout, Layer Four (Bottom) Rev Page AD9777 ...
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... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD9777BSV −40°C to +85°C AD9777BSVRL −40°C to +85°C 1 AD9777BSVZ −40°C to +85°C 1 AD9777BSZVRL −40°C to +85°C AD9777- Pb-free part. 14.20 14. ...
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NOTES Rev Page AD9777 ...
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AD9777 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02706-0-1/06(C) Rev Page ...