XC9572-7PC84C Xilinx Inc, XC9572-7PC84C Datasheet

IC CPLD 72 MCELL C-TEMP 84-PLCC

XC9572-7PC84C

Manufacturer Part Number
XC9572-7PC84C
Description
IC CPLD 72 MCELL C-TEMP 84-PLCC
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets

Specifications of XC9572-7PC84C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
69
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
122-1262
XC9572-7PC84C

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DS065 (v4.3) April 3, 2006
Features
DS065 (v4.3) April 3, 2006
Product Specification
© 1996-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
7.5 ns pin-to-pin logic delays on all pins
f
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5V in-system programmable
-
-
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP packages
CNT
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
to 125 MHz
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
5
XC9572 In-System
Programmable CPLD
Product Specification
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See
ture overview.
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
Where:
Figure 1
CC
(mA) = MC
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
(125)
Figure 1: Typical I
(65)
200
100
0
HP
LP
shows a typical calculation for the XC9572 device.
= Macrocells in low-power mode
= Macrocells in high-performance mode
HP
(1.7) + MC
Clock Frequency (MHz)
CC
vs. Frequency for XC9572
LP
50
(0.9) + MC (0.006 mA/MHz) f
Figure 2
for the architec-
DS065_01_110501
100
(160)
(100)
1

Related parts for XC9572-7PC84C

XC9572-7PC84C Summary of contents

Page 1

... Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See ture overview. Power Management Power dissipation can be reduced in the XC9572 by config- uring macrocells to standard or low-power modes of opera- tion. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for ...

Page 2

... I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC9572 Architecture www.xilinx.com 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... –3 Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com XC9572 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3.6 0 0.80 2 0.5 CCINT ...

Page 4

... XC9572 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input ...

Page 5

... T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS065 (v4.3) April 3, 2006 Product Specification XC9572 In-System Programmable CPLD XC9572-7 XC9572-10 Min Max Min - 2 1 4.5 ...

Page 6

... XC9572 In-System Programmable CPLD XC9572 I/O Pins Function Macro- Block cell PC44 PC84 PQ100 TQ100 1 1 – – – – [1] [ – 13 [1] [ – – 20 [1] [ – – – – – [ – [1] [ – 75 [1] [ – – 80 [3] [ – – – Notes: 1. Global control piN. ...

Page 7

... R XC9572 Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 5 I/O/GCK2 6 I/O/GCK3 7 I/O/GTS1 42 I/O/GTS2 40 I/O/GSR 39 TCK 17 TDI 15 TDO 30 TMS 21,41 CCINT V 3.3V/5V 32 CCIO GND 10,23,31 No Connects - DS065 (v4.3) April 3, 2006 Product Specification XC9572 In-System Programmable CPLD PC84 PQ100 38,73,78 7,59,100 22,64 ...

Page 8

... Device Part Marking and Ordering Combination Information Device Type Package Speed Operating Range Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC9572-7PC44C 7.5 ns XC9572-7PCG44C 7.5 ns XC9572-7PC84C 7.5 ns XC9572-7PCG84C 7.5 ns XC9572-7PQ100C 7.5 ns XC9572-7PQG100C 7.5 ns XC9572-7TQ100C 7.5 ns XC9572-7TQG100C 7.5 ns XC9572-10PC44C 10 ns XC9572-10PCG44C ...

Page 9

... Plastic Quad Flat Pack (PQFP) PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free TQ100 100-pin Thin Quad Flat Pack (TQFP) TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free = –40° to +85°C A Revision www.xilinx.com XC9572 In-System Programmable CPLD Operating Package Type Range ) APRPW ( ...

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