CY37128P100-125AXC Cypress Semiconductor Corp, CY37128P100-125AXC Datasheet - Page 5

• Manufacturer Part Number: CY37128P100-125AXC
• Description: IC CPLD 128 MACROCELL 100-LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37128P100-125AXC

• Number Of Macrocells: 128
• Package / Case: 100-LQFP
• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of I /o: 69
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Features: Programmable
• Voltage: 5V
• Memory Type: CMOS
• Number Of Product Terms Per Macro: 16
• Maximum Operating Frequency: 125 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 69
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Family Name: Ultra 37000
• # Macrocells: 128
• Number Of Usable Gates: 3800
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 69
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3710 - ADAPTER SOCKET PTG
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2903; CY37128P100-125AXC

Low Power Option
Each logic block can operate in high speed mode for critical path
performance, or in low power mode for power conservation. The
logic block mode is set by the user on a logic block by logic block
basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator provides
two important capabilities without affecting performance: product
term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product terms
to macrocells as needed. For example, if one macrocell requires
ten product terms while another needs just three, the product
term allocator will “steer” ten product terms to one macrocell and
three to the other. On Ultra37000 devices, product terms are
steered on an individual basis. Any number between 0 and 16
product terms can be steered to any macrocell. Note that 0
product terms is useful in cases where a particular macrocell is
unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than one
output has one or more product terms in its equation that are
common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator allows
sharing across groups of four output macrocells in a variable
fashion. The software automatically takes advantage of this
capability—the user does not have to intervene.
Note that neither product term sharing nor product term steering
have any effect on the speed of the product. All worst-case
steering and sharing configurations are incorporated in the
timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells can
either be I/O Macrocells, which include an I/O Cell which is
associated with an I/O pin, or buried Macrocells, which do not
connect to an I/O. The combination of I/O Macrocells and buried
Macrocells varies from device to device.
Buried Macrocell
Figure 2
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.
Document Number : 38-03007 Rev. *H
displays the architecture of buried macrocells. The
The register can be asynchronously set or asynchronously reset
at the logic block level with the separate set and reset product
terms. Each of these product terms features programmable
polarity. This allows the registers to be set or reset based on an
AND expression or an OR expression.
Clocking of the register is very flexible. Four global synchronous
clocks and a product term clock are available to clock the
register. Furthermore, each clock features programmable
polarity so that registers can be triggered on falling and rising
edges (see
logic block level.
The buried macrocell also supports input register capability. The
buried macrocell can be configured to act as an input register
(D-type or latch) whose input comes from the I/O pin associated
with the neighboring macrocell. The output of all buried macro-
cells is sent directly to the PIM regardless of its configuration.
I/O Macrocell
Figure 2
macrocell supports the same functions as the buried macrocell
with the addition of I/O capability. At the output of the macrocell,
a polarity control mux is available to select active LOW or active
HIGH signals. This has the added advantage of allowing signif-
icant logic reduction to occur in many applications.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated I/O
pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a high
impedance state, thus reducing system noise in bus-interface
applications. Bus-hold additionally allows unused device pins to
remain unconnected on the board, which is particularly useful
during prototyping as designers can route new signals to the
device without cutting trace connections to V
more information, see the application note Understanding
Bus-Hold—A Feature of Cypress CPLDs.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high performance
the fast edge rate provides maximum system performance.
illustrates the architecture of the I/O macrocell. The I/O
Clocking
on page 7). Clock polarity is chosen at the
Ultra37000 CPLD Family
CC
or GND. For
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