ATF1504AS-10JC44 Atmel, ATF1504AS-10JC44 Datasheet
ATF1504AS-10JC44
Specifications of ATF1504AS-10JC44
Available stocks
Related parts for ATF1504AS-10JC44
ATF1504AS-10JC44 Summary of contents
Page 1
... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High- performance Complex Programmable Logic Device ATF1504AS ATF1504ASL Rev. 0950O–PLD–7/05 1 ...
Page 2
... PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 I/O 15 GND 16 I/O/PD1 17 I/O 18 I/O/TMS 19 I/O 20 VCCIO 21 I/O 22 I/O 23 I/O 24 I/O 25 GND 26 ATF1504AS(L) 2 TDI/I/O 33 I/O 32 I/O/TDO 31 I/O 30 I/O PD1/I/O 29 VCC 28 I/O I/O/TMS 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O 60 I/O I I/O VCCIO 13 58 GND ...
Page 3
... I/O I/O/TMS 15 66 I/O I I/O I I/O/TCK VCCIO 18 63 I/O I I/O I GND I I I I/O 53 VCCIO ATF1504AS(L) 100-lead TQFP Top View 75 I/O 74 GND 73 I/O/TDO I I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I I/O 51 VCCIO 3 ...
Page 4
... SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504AS has bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable ...
Page 5
... Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user for pur- poses such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse ...
Page 6
... The XOR gate is also used to emulate T- and JK-type flip-flops. The ATF1504AS’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feed- back within a combinatorial output macrocell ...
Page 7
... Foldback Bus Figure 1. ATF1504AS Macrocell 0950O–PLD–7/05 Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The sixteen foldback terms in each region allow generation of high fan-in sum terms (up to sixteen product terms) with a nominal additional delay ...
Page 8
... I/O Diagram ATF1504AS(L) 8 The ATF1504AS offers the option of programming all input and I/O pins so that pin- keeper circuits can be utilized. When any pin is driven high or low and then subse- quently left floating, it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise ...
Page 9
... AC parameters, which include the data paths t The ATF1504AS macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power-down option, macrocells that are not used in an application can be turned-down, thereby reducing the overall power consumption of the device ...
Page 10
... I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. The ATF1504AS has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition ...
Page 11
... MIN CCIO MIN 0 MIN -4.0 mA CCIO OH Typ Max Units ATF1504AS(L) Commercial - ± 5% 3.0V - 3.6V Min Typ -2 2 -40 Com. 105 Ind. 130 Com. 10 Ind Com 85 Ind 105 Com. 4.75 Ind. 4.5 3.0 -0.3 2.0 V CCIO Com. Ind. Com. Ind. 2.4 Conditions 1.0 MHz ...
Page 12
... Minimum Array Clock Period ACNT Maximum Internal Array f ACNT Clock Frequency ATF1504AS(L) 12 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
Page 13
... OD3 3.3V pF) CCIO L Note: See ordering information for valid part numbers. Timing Model 0950O–PLD–7/05 -7 -10 -15 Min Max Min Max Min 166.7 125 100 0.5 0.5 0.5 0 0.8 0 1.5 2.5 2.0 5 5.5 ATF1504AS(L) -20 -25 Max Min Max Min Max 83 1 Units ...
Page 14
... Reduced-power Adder RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t RPA power mode. Input Test Waveforms and Measurement Levels 1.5 ns typical R F ATF1504AS( -10 -15 Min Max Min Max Min Max 4.0 5.0 4.5 5.5 9 ...
Page 15
... RPA 0950O–PLD–7/05 The ATF1504AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched internally and held ...
Page 16
... Cell (BSC) Testing BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1504AS(L) 16 The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504AS ...
Page 17
... BSC Configuration for Macrocell 0950O–PLD–7/05 Pin BSC 0 Pin 1 TDI Shift TDO OEJ OUTJ Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504AS(L) TDO D Q Capture DR Clock Pin 1 Mode 17 ...
Page 18
... The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface. The ATF1504AS allows this without contributing to system noise while delivering low output-to-output skew. Having a pro- grammable high drive option is also possible without increasing output delay or pin capacitance ...
Page 19
... OUT -5 < -25+(V IN 0.4V to 2.4V load 2.4V to 0.4V load - 5.25 2.45) for V > V OUT OUT for 0V < V < 0.71V. OUT OUT OUT ATF1504AS(L) Min 4.75 2.0 -0.5 2.4 Min Max -44 - 1.4)/0.024 OUT Equation A -142 95 V /0.023 OUT Equation B 206 + 1)/0 ...
Page 20
... ATF1504AS Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I/O/PD (1, I/O/TDI (JTAG) 1 I/O/TMS (JTAG) 7 I/O/TCK (JTAG) 26 I/O/TDO (JTAG) 32 GND 4, 16, 24 17, 29, 41 CCINT V – CCIO N/C – Signal Pins 36 # User I/O Pins 32 OE (1, 2) Global OE Pins GCLR ...
Page 21
... ATF1504AS I/O Pinouts 44- 44- 68- lead lead lead MC PLC PLCC TQFP PLCC – – – PD1 – – – – – TDI 9 A – – – – – – – – – – – – – – – – – – – ...
Page 22
... FREQUENCY (MHz) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V 25°C) A 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 4.50 4.75 5.00 SUPPLY VOLTAGE (V) ATF1504AS(L) 22 REDUCED POWER MODE 5.25 5.50 5.25 5.50 = 25°C) A 80.00 100.00 5.25 5.50 SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (T = 25° ...
Page 23
... OUTPUT VOLTAGE (V) 0950O–PLD–7/05 = 25°C) 5.25 5.50 = 25°C) A 5.3 5.5 3.5 4.0 4.5 5.0 3.00 3.50 4.00 4.50 5.00 ATF1504AS(L) NORMALIZED TPD VS. TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) NORMALIZED TCO VS. SUPPLY VOLTAGE (T = 25°C) A 1.2 1 ...
Page 24
... NORMALIZED TCO VS.TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 TEMPERATURE (C) ATF1504AS( 5.0V) 25.0 75.0 = 5.0V) 25.0 75.0 0950O–PLD–7/05 ...
Page 25
... Ordering Information ATF1504AS Standard Package Options CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 10 5 125 15 8 100 15 8 100 Notes: 1. The last time buy date is Sept. 30, 2005 for shaded parts. 2. For the QC100 package, customers may migrate to the ATF1508AS-10QU100 or AU100. ...
Page 26
... ATF1504AS Green Package Options (Pb/Halide-free/RoHS Compliant CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 68J 68-lead, Plastic J-leaded Chip Carrier (PLCC) 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) ...
Page 27
... The last time buy date is Sept. 30, 2005 for shaded parts. Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” “I”) and de-rate power by 30%. ATF1504ASL Green Package Options (Pb/Halide-free/RoHS Compliant ...
Page 28
... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS( TITLE 44A, 44-lead Body Size, 1 ...
Page 29
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0950O–PLD–7/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1504AS(L) 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
Page 30
... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS(L) 30 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...
Page 31
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0950O–PLD–7/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1504AS(L) 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
Page 32
... PQFP PIN 1 ID PIN 0º~7º C 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS( TITLE 100Q1, 100-lead Body, 3.2 mm Footprint, 0.65 mm Pitch, Plastic Quad Flat Package (PQFP) COMMON DIMENSIONS (Unit of Measure = mm) JEDEC STANDARD MS-022, GC-1 SYMBOL MIN NOM MAX NOTE A – ...
Page 33
... Orchard Parkway San Jose, CA 95131 R 0950O–PLD–7/05 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1504AS( COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.05 – ...
Page 34
... Revision History ATF1504AS(L) 34 Revision Comments Green package options added. 0950O 0950O–PLD–7/05 ...
Page 35
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...